Re: [Xen-devel] [PATCH 19/27] xen/arm: page: Clean-up the definition of MAIRVAL

2017-08-23 Thread Julien Grall



On 08/23/2017 12:42 PM, Andre Przywara wrote:

Hi,


Hi Andre,


On 14/08/17 15:24, Julien Grall wrote:

Currently MAIRVAL is defined in term of MAIR0VAL and MAIR1VAL which are
both hardcoded value. This makes quite difficult to understand the value
written in both registers.

Rework the definition by using value of each attribute shifted by their
associated index.

Signed-off-by: Julien Grall 


I checked all the bits and encoding against the ARMv8 ARM, they look
correct to me.
However I feel that the attribute renaming patch (20/27) should come
before this one.


I can invert the two patches. I don't plan to keep your tags in both 
patches as this would sensibly change some bits.


Cheers,

--
Julien Grall

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Re: [Xen-devel] [PATCH 19/27] xen/arm: page: Clean-up the definition of MAIRVAL

2017-08-23 Thread Andre Przywara
Hi,

On 14/08/17 15:24, Julien Grall wrote:
> Currently MAIRVAL is defined in term of MAIR0VAL and MAIR1VAL which are
> both hardcoded value. This makes quite difficult to understand the value
> written in both registers.
> 
> Rework the definition by using value of each attribute shifted by their
> associated index.
> 
> Signed-off-by: Julien Grall 

I checked all the bits and encoding against the ARMv8 ARM, they look
correct to me.
However I feel that the attribute renaming patch (20/27) should come
before this one.
However:

Reviewed-by: Andre Przywara 

Cheers,
Andre.

> ---
>  xen/include/asm-arm/page.h | 43 +--
>  1 file changed, 25 insertions(+), 18 deletions(-)
> 
> diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h
> index d7a048b64d..86b227c291 100644
> --- a/xen/include/asm-arm/page.h
> +++ b/xen/include/asm-arm/page.h
> @@ -22,6 +22,21 @@
>  #define LPAE_SH_INNER 0x3
>  
>  /*
> + * Attribute Indexes.
> + *
> + * These are valid in the AttrIndx[2:0] field of an LPAE stage 1 page
> + * table entry. They are indexes into the bytes of the MAIR*
> + * registers, as defined above.
> + *
> + */
> +#define MT_UNCACHED  0x0
> +#define MT_BUFFERABLE0x1
> +#define MT_WRITETHROUGH  0x2
> +#define MT_WRITEBACK 0x3
> +#define MT_DEV_SHARED0x4
> +#define MT_WRITEALLOC0x7
> +
> +/*
>   * LPAE Memory region attributes. Indexed by the AttrIndex bits of a
>   * LPAE entry; the 8-bit fields are packed little-endian into MAIR0 and 
> MAIR1.
>   *
> @@ -35,26 +50,18 @@
>   *   reserved 110
>   *   MT_WRITEALLOC111      -- Write-back write-allocate
>   *
> - *   MT_DEV_WC001   (== BUFFERABLE)
>   */
> -#define MAIR0VAL 0xeeaa4400
> -#define MAIR1VAL 0xff04
> -#define MAIRVAL (MAIR0VAL|MAIR1VAL<<32)
> +#define MAIR(attr, mt) (_AC(attr, ULL) << ((mt) * 8))
>  
> -/*
> - * Attribute Indexes.
> - *
> - * These are valid in the AttrIndx[2:0] field of an LPAE stage 1 page
> - * table entry. They are indexes into the bytes of the MAIR*
> - * registers, as defined above.
> - *
> - */
> -#define MT_UNCACHED  0x0
> -#define MT_BUFFERABLE0x1
> -#define MT_WRITETHROUGH  0x2
> -#define MT_WRITEBACK 0x3
> -#define MT_DEV_SHARED0x4
> -#define MT_WRITEALLOC0x7
> +#define MAIRVAL (MAIR(0x00, MT_UNCACHED) | \
> + MAIR(0x44, MT_BUFFERABLE)   | \
> + MAIR(0xaa, MT_WRITETHROUGH) | \
> + MAIR(0xee, MT_WRITEBACK)| \
> + MAIR(0x04, MT_DEV_SHARED)   | \
> + MAIR(0xff, MT_WRITEALLOC))
> +
> +#define MAIR0VAL (MAIRVAL & 0x)
> +#define MAIR1VAL (MAIRVAL >> 32)
>  
>  #define PAGE_HYPERVISOR (MT_WRITEALLOC)
>  #define PAGE_HYPERVISOR_NOCACHE (MT_DEV_SHARED)
> 

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[Xen-devel] [PATCH 19/27] xen/arm: page: Clean-up the definition of MAIRVAL

2017-08-14 Thread Julien Grall
Currently MAIRVAL is defined in term of MAIR0VAL and MAIR1VAL which are
both hardcoded value. This makes quite difficult to understand the value
written in both registers.

Rework the definition by using value of each attribute shifted by their
associated index.

Signed-off-by: Julien Grall 
---
 xen/include/asm-arm/page.h | 43 +--
 1 file changed, 25 insertions(+), 18 deletions(-)

diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h
index d7a048b64d..86b227c291 100644
--- a/xen/include/asm-arm/page.h
+++ b/xen/include/asm-arm/page.h
@@ -22,6 +22,21 @@
 #define LPAE_SH_INNER 0x3
 
 /*
+ * Attribute Indexes.
+ *
+ * These are valid in the AttrIndx[2:0] field of an LPAE stage 1 page
+ * table entry. They are indexes into the bytes of the MAIR*
+ * registers, as defined above.
+ *
+ */
+#define MT_UNCACHED  0x0
+#define MT_BUFFERABLE0x1
+#define MT_WRITETHROUGH  0x2
+#define MT_WRITEBACK 0x3
+#define MT_DEV_SHARED0x4
+#define MT_WRITEALLOC0x7
+
+/*
  * LPAE Memory region attributes. Indexed by the AttrIndex bits of a
  * LPAE entry; the 8-bit fields are packed little-endian into MAIR0 and MAIR1.
  *
@@ -35,26 +50,18 @@
  *   reserved 110
  *   MT_WRITEALLOC111      -- Write-back write-allocate
  *
- *   MT_DEV_WC001   (== BUFFERABLE)
  */
-#define MAIR0VAL 0xeeaa4400
-#define MAIR1VAL 0xff04
-#define MAIRVAL (MAIR0VAL|MAIR1VAL<<32)
+#define MAIR(attr, mt) (_AC(attr, ULL) << ((mt) * 8))
 
-/*
- * Attribute Indexes.
- *
- * These are valid in the AttrIndx[2:0] field of an LPAE stage 1 page
- * table entry. They are indexes into the bytes of the MAIR*
- * registers, as defined above.
- *
- */
-#define MT_UNCACHED  0x0
-#define MT_BUFFERABLE0x1
-#define MT_WRITETHROUGH  0x2
-#define MT_WRITEBACK 0x3
-#define MT_DEV_SHARED0x4
-#define MT_WRITEALLOC0x7
+#define MAIRVAL (MAIR(0x00, MT_UNCACHED) | \
+ MAIR(0x44, MT_BUFFERABLE)   | \
+ MAIR(0xaa, MT_WRITETHROUGH) | \
+ MAIR(0xee, MT_WRITEBACK)| \
+ MAIR(0x04, MT_DEV_SHARED)   | \
+ MAIR(0xff, MT_WRITEALLOC))
+
+#define MAIR0VAL (MAIRVAL & 0x)
+#define MAIR1VAL (MAIRVAL >> 32)
 
 #define PAGE_HYPERVISOR (MT_WRITEALLOC)
 #define PAGE_HYPERVISOR_NOCACHE (MT_DEV_SHARED)
-- 
2.11.0


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