Hi Ian,
On 05/03/2015 14:43, Ian Campbell wrote:
On Wed, 2015-02-18 at 15:16 +, Julien Grall wrote:
ranges; means there is not translation necessary. But nothing prevent
to have a the property ranges set.
I don't suppose you know of a system where this translation is needed do
you? So
Hi Ian,
On 18/02/2015 13:50, Ian Campbell wrote:
On Tue, 2015-02-17 at 17:33 +, Julien Grall wrote:
Hi Ian,
On 24/10/14 10:58, Ian Campbell wrote:
These properties are defined in ePAPR and the OpenFirmware PCI Bus Binding
Specification (IEEE Std 1275-1994).
This replaces the xgene
On Wed, 2015-02-18 at 14:19 +, Julien Grall wrote:
Hi Ian,
On 18/02/2015 13:50, Ian Campbell wrote:
On Tue, 2015-02-17 at 17:33 +, Julien Grall wrote:
Hi Ian,
On 24/10/14 10:58, Ian Campbell wrote:
These properties are defined in ePAPR and the OpenFirmware PCI Bus Binding
On 18/02/2015 15:18, Ian Campbell wrote:
On Wed, 2015-02-18 at 15:05 +, Julien Grall wrote:
On 18/02/2015 14:37, Ian Campbell wrote:
On Wed, 2015-02-18 at 14:19 +, Julien Grall wrote:
I think so, and we probably should consider the two cases separately
since the right answer could
On Wed, 2015-02-18 at 15:31 +, Julien Grall wrote:
Either soc has a device_type property which we understand, in which case
we would handle it and stop recursing or (more likely for an soc) it
does not, in which case we would handle the pcie ranges property, but it
needs to be
On Tue, 2015-02-17 at 17:33 +, Julien Grall wrote:
Hi Ian,
On 24/10/14 10:58, Ian Campbell wrote:
These properties are defined in ePAPR and the OpenFirmware PCI Bus Binding
Specification (IEEE Std 1275-1994).
This replaces the xgene specific mapping. Tested on Mustang and on a
On 18/02/2015 14:37, Ian Campbell wrote:
On Wed, 2015-02-18 at 14:19 +, Julien Grall wrote:
I think so, and we probably should consider the two cases separately
since the right answer could reasonably differ for different resource
types.
I am reasonably convinced that for MMIO (+IO+CFG
On Wed, 2015-02-18 at 15:05 +, Julien Grall wrote:
On 18/02/2015 14:37, Ian Campbell wrote:
On Wed, 2015-02-18 at 14:19 +, Julien Grall wrote:
I think so, and we probably should consider the two cases separately
since the right answer could reasonably differ for different resource
On Wed, 2015-02-18 at 15:13 +, Julien Grall wrote:
On 18/02/2015 14:37, Ian Campbell wrote:
I am reasonably convinced that for MMIO (+IO+CFG space) we should map
everything as described by the ranges property of the top most node, it
can be considered an analogue to / extension of the
On 18/02/2015 14:37, Ian Campbell wrote:
I am reasonably convinced that for MMIO (+IO+CFG space) we should map
everything as described by the ranges property of the top most node, it
can be considered an analogue to / extension of the reg property of that
node.
BTW, the CFG space is part of
On 18/02/2015 15:05, Julien Grall wrote:
On 18/02/2015 14:37, Ian Campbell wrote:
On Wed, 2015-02-18 at 14:19 +, Julien Grall wrote:
I think so, and we probably should consider the two cases separately
since the right answer could reasonably differ for different resource
types.
I am
Hi Ian,
On 24/10/14 10:58, Ian Campbell wrote:
These properties are defined in ePAPR and the OpenFirmware PCI Bus Binding
Specification (IEEE Std 1275-1994).
This replaces the xgene specific mapping. Tested on Mustang and on a model
with
a PCI virtio controller.
I'm wondering why you
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