If MCG_LMCE_P is present in guest MSR_IA32_MCG_CAP, then set LMCE and
LOCK bits in guest MSR_IA32_FEATURE_CONTROL. Intel SDM requires those
bits are set before SW can enable LMCE.
Signed-off-by: Haozhong Zhang
---
Cc: Jan Beulich
Cc: Andrew Cooper
Cc: Jun Nakajima
Cc: Kevin Tian
Changes in v2:
* Remove unnecessary !! in vmce_support_lmce().
* Rename "struct vcpu *v" to "struct vcpu *curr" in vmx_msr_read_intercept().
* Remove the duplicated neseted VMX check in vmx_msr_read_intercept().
---
xen/arch/x86/cpu/mcheck/mce_intel.c | 4
xen/arch/x86/hvm/vmx/vmx.c | 9 +
xen/arch/x86/hvm/vmx/vvmx.c | 4
xen/include/asm-x86/mce.h | 1 +
4 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c
b/xen/arch/x86/cpu/mcheck/mce_intel.c
index f8cf5e6..bf0e8ff 100644
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -955,3 +955,7 @@ int vmce_intel_rdmsr(const struct vcpu *v, uint32_t msr,
uint64_t *val)
return 1;
}
+bool vmce_support_lmce(const struct vcpu *v)
+{
+return v->arch.vmce.mcg_cap & MCG_LMCE_P;
+}
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 894d7d4..301fda0 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -55,6 +55,7 @@
#include
#include
#include
+#include
#include
#include
@@ -2753,6 +2754,8 @@ static int is_last_branch_msr(u32 ecx)
static int vmx_msr_read_intercept(unsigned int msr, uint64_t *msr_content)
{
+struct vcpu *curr = current;
+
HVM_DBG_LOG(DBG_LEVEL_MSR, "ecx=%#x", msr);
switch ( msr )
@@ -2770,6 +2773,12 @@ static int vmx_msr_read_intercept(unsigned int msr,
uint64_t *msr_content)
__vmread(GUEST_IA32_DEBUGCTL, msr_content);
break;
case MSR_IA32_FEATURE_CONTROL:
+*msr_content = IA32_FEATURE_CONTROL_LOCK;
+if ( vmce_support_lmce(curr) )
+*msr_content |= IA32_FEATURE_CONTROL_LMCE_ON;
+if ( nestedhvm_enabled(curr->domain) )
+*msr_content |= IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX;
+break;
case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_VMFUNC:
if ( !nvmx_msr_read_intercept(msr, msr_content) )
goto gp_fault;
diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index e2c0951..4aa70ef 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -2068,10 +2068,6 @@ int nvmx_msr_read_intercept(unsigned int msr, u64
*msr_content)
data = gen_vmx_msr(data, VMX_ENTRY_CTLS_DEFAULT1, host_data);
break;
-case MSR_IA32_FEATURE_CONTROL:
-data = IA32_FEATURE_CONTROL_LOCK |
- IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX;
-break;
case MSR_IA32_VMX_VMCS_ENUM:
/* The max index of VVMCS encoding is 0x1f. */
data = 0x1f << 1;
diff --git a/xen/include/asm-x86/mce.h b/xen/include/asm-x86/mce.h
index 549bef3..6b827ef 100644
--- a/xen/include/asm-x86/mce.h
+++ b/xen/include/asm-x86/mce.h
@@ -36,6 +36,7 @@ extern void vmce_init_vcpu(struct vcpu *);
extern int vmce_restore_vcpu(struct vcpu *, const struct hvm_vmce_vcpu *);
extern int vmce_wrmsr(uint32_t msr, uint64_t val);
extern int vmce_rdmsr(uint32_t msr, uint64_t *val);
+extern bool vmce_support_lmce(const struct vcpu *v);
extern unsigned int nr_mce_banks;
--
2.10.1
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