Re: [Xen-devel] [PATCH v2 4/7] x86: put msr-index.h in uapi

[Andy Shevchenko]

On Fri, Jan 6, 2017 at 11:43 AM, Nicolas Dichtel
 wrote:
> This header file is exported, thus move it to uapi.

Just hint for the future:
-M (move)
-C (copy)
-D (delete) [though this is NOT for applying]

-- 
With Best Regards,
Andy Shevchenko

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Re: [Xen-devel] [PATCH v2 4/7] x86: put msr-index.h in uapi

[Borislav Petkov]

On Fri, Jan 06, 2017 at 10:43:56AM +0100, Nicolas Dichtel wrote:
> This header file is exported, thus move it to uapi.

It should rather not be exported - please remove it from
arch/x86/include/uapi/asm/Kbuild instead.

Thanks.

-- 
Regards/Gruss,
Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

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[Xen-devel] [PATCH v2 4/7] x86: put msr-index.h in uapi

[Nicolas Dichtel]

This header file is exported, thus move it to uapi.

Signed-off-by: Nicolas Dichtel 
---
 arch/x86/include/asm/msr-index.h  | 694 +
 arch/x86/include/uapi/asm/msr-index.h | 698 ++
 2 files changed, 699 insertions(+), 693 deletions(-)
 create mode 100644 arch/x86/include/uapi/asm/msr-index.h

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 710273c617b8..1baa0628da74 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -1,698 +1,6 @@
 #ifndef _ASM_X86_MSR_INDEX_H
 #define _ASM_X86_MSR_INDEX_H
 
-/*
- * CPU model specific register (MSR) numbers.
- *
- * Do not add new entries to this file unless the definitions are shared
- * between multiple compilation units.
- */
-
-/* x86-64 specific MSRs */
-#define MSR_EFER   0xc080 /* extended feature register */
-#define MSR_STAR   0xc081 /* legacy mode SYSCALL target */
-#define MSR_LSTAR  0xc082 /* long mode SYSCALL target */
-#define MSR_CSTAR  0xc083 /* compat mode SYSCALL target */
-#define MSR_SYSCALL_MASK   0xc084 /* EFLAGS mask for syscall */
-#define MSR_FS_BASE0xc100 /* 64bit FS base */
-#define MSR_GS_BASE0xc101 /* 64bit GS base */
-#define MSR_KERNEL_GS_BASE 0xc102 /* SwapGS GS shadow */
-#define MSR_TSC_AUX0xc103 /* Auxiliary TSC */
-
-/* EFER bits: */
-#define _EFER_SCE  0  /* SYSCALL/SYSRET */
-#define _EFER_LME  8  /* Long mode enable */
-#define _EFER_LMA  10 /* Long mode active (read-only) */
-#define _EFER_NX   11 /* No execute enable */
-#define _EFER_SVME 12 /* Enable virtualization */
-#define _EFER_LMSLE13 /* Long Mode Segment Limit Enable */
-#define _EFER_FFXSR14 /* Enable Fast FXSAVE/FXRSTOR */
-
-#define EFER_SCE   (1<<_EFER_SCE)
-#define EFER_LME   (1<<_EFER_LME)
-#define EFER_LMA   (1<<_EFER_LMA)
-#define EFER_NX(1<<_EFER_NX)
-#define EFER_SVME  (1<<_EFER_SVME)
-#define EFER_LMSLE (1<<_EFER_LMSLE)
-#define EFER_FFXSR (1<<_EFER_FFXSR)
-
-/* Intel MSRs. Some also available on other CPUs */
-
-#define MSR_PPIN_CTL   0x004e
-#define MSR_PPIN   0x004f
-
-#define MSR_IA32_PERFCTR0  0x00c1
-#define MSR_IA32_PERFCTR1  0x00c2
-#define MSR_FSB_FREQ   0x00cd
-#define MSR_PLATFORM_INFO  0x00ce
-
-#define MSR_NHM_SNB_PKG_CST_CFG_CTL0x00e2
-#define NHM_C3_AUTO_DEMOTE (1UL << 25)
-#define NHM_C1_AUTO_DEMOTE (1UL << 26)
-#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
-#define SNB_C1_AUTO_UNDEMOTE   (1UL << 27)
-#define SNB_C3_AUTO_UNDEMOTE   (1UL << 28)
-
-#define MSR_MTRRcap0x00fe
-#define MSR_IA32_BBL_CR_CTL0x0119
-#define MSR_IA32_BBL_CR_CTL3   0x011e
-
-#define MSR_IA32_SYSENTER_CS   0x0174
-#define MSR_IA32_SYSENTER_ESP  0x0175
-#define MSR_IA32_SYSENTER_EIP  0x0176
-
-#define MSR_IA32_MCG_CAP   0x0179
-#define MSR_IA32_MCG_STATUS0x017a
-#define MSR_IA32_MCG_CTL   0x017b
-#define MSR_IA32_MCG_EXT_CTL   0x04d0
-
-#define MSR_OFFCORE_RSP_0  0x01a6
-#define MSR_OFFCORE_RSP_1  0x01a7
-#define MSR_TURBO_RATIO_LIMIT  0x01ad
-#define MSR_TURBO_RATIO_LIMIT1 0x01ae
-#define MSR_TURBO_RATIO_LIMIT2 0x01af
-
-#define MSR_LBR_SELECT 0x01c8
-#define MSR_LBR_TOS0x01c9
-#define MSR_LBR_NHM_FROM   0x0680
-#define MSR_LBR_NHM_TO 0x06c0
-#define MSR_LBR_CORE_FROM  0x0040
-#define MSR_LBR_CORE_TO0x0060
-
-#define MSR_LBR_INFO_0 0x0dc0 /* ... 0xddf for _31 */
-#define LBR_INFO_MISPRED   BIT_ULL(63)
-#define LBR_INFO_IN_TX BIT_ULL(62)
-#define LBR_INFO_ABORT BIT_ULL(61)
-#define LBR_INFO_CYCLES0x
-
-#define MSR_IA32_PEBS_ENABLE   0x03f1
-#define MSR_IA32_DS_AREA   0x0600
-#define MSR_IA32_PERF_CAPABILITIES 0x0345
-#define MSR_PEBS_LD_LAT_THRESHOLD  0x03f6
-
-#define MSR_IA32_RTIT_CTL  0x0570
-#define MSR_IA32_RTIT_STATUS   0x0571
-#define MSR_IA32_RTIT_ADDR0_A  0x0580
-#define MSR_IA32_RTIT_ADDR0_B  0x0581
-#define MSR_IA32_RTIT_ADDR1_A  0x0582
-#define MSR_IA32_RTIT_ADDR1_B  0x0583
-#define MSR_IA32_RTIT_ADDR2_A  0x0584
-#define MSR_IA32_RTIT_ADDR2_B  0x0585
-#define