This exposes less code pieces and at the same time reduces the range
covered from slightly above 3 pages to a little below 2 of them.
The code being moved is entirely unchanged, except for the removal of
trailing blanks and a pointless q suffix from "retq".
A few more small pieces could be
Now that we zero all registers early on all entry paths, use that to
avoid a couple of immediates here.
Signed-off-by: Jan Beulich
---
We may want to consider eliminating a few more $0 this way. But
especially for byte ones I'm not sure it's worth it, due to the REX
prefix the
On 08/03/18 11:17, Jan Beulich wrote:
On 02.03.18 at 09:14, wrote:
>> --- a/xen/arch/x86/mm.c
>> +++ b/xen/arch/x86/mm.c
>> @@ -510,15 +510,19 @@ void make_cr3(struct vcpu *v, mfn_t mfn)
>>
>> void write_ptbase(struct vcpu *v)
>> {
>> -if ( this_cpu(root_pgt) &&
On 08/03/18 11:15, Jan Beulich wrote:
> Instead of using RDMSR/WRMSR, on fsgsbase-capable systems use a double
> SWAPGS combined with RDGSBASE/WRGSBASE. This halves execution time for
> a shadow GS update alone on my Haswell (and we have indications of
> good performance improvements by this on
Instead of using RDMSR/WRMSR, on fsgsbase-capable systems use a double
SWAPGS combined with RDGSBASE/WRGSBASE. This halves execution time for
a shadow GS update alone on my Haswell (and we have indications of
good performance improvements by this on Skylake too), while the win is
even higher when
Travis reports:
sched_rt.c:241:30: error: unused function 'rt_dom' [-Werror,-Wunused-function]
static inline struct rt_dom *rt_dom(const struct domain *dom)
^
1 error generated.
when compiling with Clang. Drop the function.
Signed-off-by: Andrew Cooper
Hello,
On 08/03/18 06:15, Peng Fan wrote:
Hi Stefano,
On Fri, Mar 02, 2018 at 11:05:54AM -0800, Stefano Stabellini wrote:
Hi all,
This series changes the initialization of two virtual registers to make
sure they match the value of the underlying physical cpu.
It also disables cpus different
All uploaded PM data from non-dom0 CPUs takes the info from vCPU 0 and
changing only the acpi_id. For processors which P-state coordination type
is HW_ALL (0xFD) it is OK to upload bogus P-state dependency information
(_PSD), because Xen will ignore any cpufreq domains created for past CPUs.
>>> On 02.03.18 at 09:14, wrote:
> --- a/xen/arch/x86/mm.c
> +++ b/xen/arch/x86/mm.c
> @@ -510,15 +510,19 @@ void make_cr3(struct vcpu *v, mfn_t mfn)
>
> void write_ptbase(struct vcpu *v)
> {
> -if ( this_cpu(root_pgt) && is_pv_vcpu(v) && !is_pv_32bit_vcpu(v) )
> +if
flight 120342 xen-unstable-smoke real [real]
http://logs.test-lab.xenproject.org/osstest/logs/120342/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
build-arm64-xsm 6 xen-buildfail REGR. vs. 120304
build-armhf
On 03/07/2018 07:41 PM, Andrew Cooper wrote:
> The OSSTest smoke tests reports:
>
> sched_credit2.c: In function 'csched2_alloc_domdata':
> sched_credit2.c:3015:9: error: implicit declaration of function 'ERR_PTR'
> [-Werror=implicit-function-declaration]
>return
On Wed, 2018-03-07 at 12:04 -0800, Stefano Stabellini wrote:
> On Wed, 7 Mar 2018, Andrew Cooper wrote:
> > The OSSTest smoke tests reports:
> >
> > sched_credit2.c: In function 'csched2_alloc_domdata':
> > sched_credit2.c:3015:9: error: implicit declaration of function
> 'ERR_PTR'
>>> On 05.03.18 at 16:56, wrote:
> On 28/02/18 13:03, Jan Beulich wrote:
>> @@ -5178,18 +5202,33 @@ x86_emulate(
>> _regs.eflags |= X86_EFLAGS_AC;
>> break;
>>
>> -#ifdef __XEN__
>> -case 0xd1: /* xsetbv */
>> +case 0xd0:
>>> On 07.03.18 at 21:52, wrote:
> When starting a guest with the 'xl create' command (non-verbose) i get
> this extra output on PVH guest types only:
>
> S3 disabled
> S4 disabled
> CONV disabled
>
>
> It seems libacpi/* only contains normal printf's, so for the other
>>> On 07.03.18 at 20:12, wrote:
> --- a/xen/common/domain.c
> +++ b/xen/common/domain.c
> @@ -399,6 +399,9 @@ struct domain *domain_create(domid_t domid, unsigned int
> domcr_flags,
> return d;
>
> fail:
> +ASSERT(err < 0); /* Sanity check paths
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