On Wed, May 31, 2023 at 11:15:44AM +0200, Jan Beulich wrote:
> On 30.05.2023 18:02, Roger Pau Monné wrote:
> > On Wed, Apr 05, 2023 at 12:15:26PM +0200, Jan Beulich wrote:
> >> On 31.03.2023 11:59, Roger Pau Monne wrote:
> >>> Only set the GOP mode if vga is selected in the console option,
> >>
> >
On 31.05.2023 00:38, Stefano Stabellini wrote:
> On Fri, 26 May 2023, Jan Beulich wrote:
>> On 25.05.2023 21:24, Stefano Stabellini wrote:
>>> On Thu, 25 May 2023, Jan Beulich wrote:
On 25.05.2023 01:37, Stefano Stabellini wrote:
> On Wed, 24 May 2023, Jan Beulich wrote:
RFC: _set
On 30.05.2023 18:02, Roger Pau Monné wrote:
> On Wed, Apr 05, 2023 at 12:15:26PM +0200, Jan Beulich wrote:
>> On 31.03.2023 11:59, Roger Pau Monne wrote:
>>> Only set the GOP mode if vga is selected in the console option,
>>
>> This particular aspect of the behavior is inconsistent with legacy
>> b
On 30.05.2023 22:06, Olaf Hering wrote:
> Tue, 30 May 2023 10:41:07 +0200 Jan Beulich :
>
>> Using this N would be correct afaict, but that N isn't num_online_cpus().
>> CPUs may have been offlined by the time trace buffers are initialized, so
>> without looking too closely I think it would be num
On Tue, May 30, 2023 at 06:31:03PM +0100, Andrew Cooper wrote:
> I've committed this, but made two tweaks to the commit message. First,
> "x86/hvm" in the subject because it's important context at a glance.
Sure, that makes sense.
> Second, I've adjusted the bit about PV guests. The reason why w
On Tue, May 30, 2023 at 06:29:14PM +0100, Andrew Cooper wrote:
> ... I've changed this on commit to just "Automatic IBRS". The behaviour
> is more far complicated than this, and anyone who wants to know needs to
> read the manual extra carefully.
>
> For one, there's a behaviour which depends on
On Wed, May 31, 2023 at 09:28:57AM +0200, Juergen Gross wrote:
> Can you please boot the system with the MTRR patches and specify "mtrr=debug"
> on the command line? I'd be interested in the raw register values being read
> and the resulting memory type map.
This is exactly why I wanted this optio
flight 181019 xen-unstable real [real]
flight 181025 xen-unstable real-retest [real]
http://logs.test-lab.xenproject.org/osstest/logs/181019/
http://logs.test-lab.xenproject.org/osstest/logs/181025/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be r
On Wed, May 31, 2023 at 09:49:32AM +0200, Marek Marczykowski-Górecki wrote:
> Hi,
>
> I returned to HVM performance once again, this time looking at PCI
> passthrough impact evaluating network throughput.
> The setup:
> - Xen 4.17
> - Linux 6.3.2 in all domU
> - iperf -c running in a PVH (call
Hi,
I returned to HVM performance once again, this time looking at PCI
passthrough impact evaluating network throughput.
The setup:
- Xen 4.17
- Linux 6.3.2 in all domU
- iperf -c running in a PVH (call it "client")
- iperf -s running in a HVM (call it "server")
- client's netfront has a back
The decision to allow parallel bringup of secondary CPUs checks
CC_ATTR_GUEST_STATE_ENCRYPT to detect encrypted guests. Those cannot use
parallel bootup because accessing the local APIC is intercepted and raises
a #VC or #VE, which cannot be handled at that point.
The check works correctly, but on
On Tue, May 30, 2023 at 02:09:58PM -0400, Stefan Hajnoczi wrote:
Stop using the .bdrv_co_io_plug() API because it is not multi-queue
block layer friendly. Use the new blk_io_plug_call() API to batch I/O
submission instead.
Note that a dev_max_batch check is dropped in laio_io_unplug() because
th
On 30.05.23 17:28, Borislav Petkov wrote:
On Mon, May 22, 2023 at 04:17:50PM +0200, Juergen Gross wrote:
The attached diff is for patch 13.
Merged and pushed out into same branch.
Next issue. Diffing /proc/mtrr shows:
--- proc-mtrr.6.3 2023-05-30 17:00:13.215999483 +0200
+++ proc-mtrr.
Arm now can use the "dom0=" Xen command line option and the support
for guests running SVE instructions is added, put entries in the
changelog.
Mention the "Tech Preview" status and add an entry in SUPPORT.md
Signed-off-by: Luca Fancellu
Acked-by: Henry Wang # CHANGELOG
Reviewed-by: Bertrand Ma
Add sve parameter in XL configuration to allow guests to use
SVE feature.
Signed-off-by: Luca Fancellu
Reviewed-by: Anthony PERARD
---
Changes from v7:
- add R-by Anthony
Changes from v6:
- Add check for sve_vl be multiple of 128 (Anthony)
Changes from v5:
- Update documentation
- re-generat
On Arm, the SVE vector length is encoded in arch_capabilities field
of struct xen_sysctl_physinfo, make use of this field in the tools
when building for arm.
Create header arm-arch-capabilities.h to handle the arch_capabilities
field of physinfo for Arm.
Signed-off-by: Luca Fancellu
Acked-by: Ge
Add a device tree property in the dom0less domU configuration
to enable the guest to use SVE.
Update documentation.
Signed-off-by: Luca Fancellu
Reviewed-by: Bertrand Marquis
Reviewed-by: Michal Orzel
Acked-by: Julien Grall
---
Changes from v7:
- Add r-by Bertrand and Michal
- Fixed some pa
Add a command line parameter to allow Dom0 the use of SVE resources,
the command line parameter sve=, sub argument of dom0=,
controls the feature on this domain and sets the maximum SVE vector
length for Dom0.
Add a new function, parse_signed_integer(), to parse an integer
command line argument.
Add sve_vl field to arch_domain and xen_arch_domainconfig struct,
to allow the domain to have an information about the SVE feature
and the number of SVE register bits that are allowed for this
domain.
sve_vl field is the vector length in bits divided by 128, this
allows to use less space in the st
When the arm platform supports SVE, advertise the feature in the
field arch_capabilities in struct xen_sysctl_physinfo by encoding
the SVE vector length in it.
Signed-off-by: Luca Fancellu
Reviewed-by: Bertrand Marquis
---
Changes from v5:
- Add R-by from Bertrand
Changes from v4:
- Write arch
Enable Xen to handle the SVE extension, add code in cpufeature module
to handle ZCR SVE register, disable trapping SVE feature on system
boot only when SVE resources are accessed.
While there, correct coding style for the comment on coprocessor
trapping.
Now cptr_el2 is part of the domain context
Currently x86 defines a Xen command line argument dom0= where
there can be specified dom0 controlling sub-options, to use it also
on Arm, move the code that loops through the list of arguments from
x86 to the common code and from there, call architecture specific
functions to handle the comma separ
Save/restore context switch for SVE, allocate memory to contain
the Z0-31 registers whose length is maximum 2048 bits each and
FFR who can be maximum 256 bits, the allocated memory depends on
how many bits is the vector length for the domain and how many bits
are supported by the platform.
Save P0
SVE has a new exception class with code 0x19, introduce the new code
and handle the exception.
Signed-off-by: Luca Fancellu
Reviewed-by: Bertrand Marquis
Reviewed-by: Julien Grall
---
Changes from v6:
- Add R-by Julien
Changes from v5:
- modified error messages (Julien)
- add R-by Bertrand
C
When a guest is allowed to use SVE, expose the SVE features through
the identification registers.
Signed-off-by: Luca Fancellu
Acked-by: Julien Grall
Reviewed-by: Bertrand Marquis
---
Changes from v7:
- add r-by Bertrand
Changes from v6:
- code style fix, add A-by Julien
Changes from v5:
- g
This serie is introducing the possibility for Dom0 and DomU guests to use
sve/sve2 instructions.
SVE feature introduces new instruction and registers to improve performances on
floating point operations.
The SVE feature is advertised using the ID_AA64PFR0_EL1 register, SVE field, and
when availab
flight 181024 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/181024/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf d8e5d35ede7158ccbb9abf600e65b9aa6e043f74
baseline version:
ovmf 0f9283429dd487deeeb26
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