On Fri, Apr 25, 2025 at 04:35:06PM -0700, Stefano Stabellini wrote:
> From: Andrei Cherechesu
>
> Normally, the Imagebuilder would precompute the sizes of the loaded
> binaries and addresses where they are loaded before generating the
> script, and the sizes and addresses that needed to be provid
From: Federico Serafini
Tag MISRA C Rule 19.1 as clean to avoid regressions.
Signed-off-by: Federico Serafini
Signed-off-by: Victor Lira
---
Cc: Andrew Cooper
Cc: Anthony PERARD
Cc: Michal Orzel
Cc: Jan Beulich
Cc: Julien Grall
Cc: Roger Pau Monné
Cc: Stefano Stabellini
Cc: Nicola Vetri
On 4/23/25 15:27, Jason Andryuk wrote:
On 2025-04-19 18:08, Daniel P. Smith wrote:
The bzimage logic uses the unit global orig_image_len to hold the
original
module length for the kernel when the headroom is calculated. It then
uses
orig_image_len to locate the start of the bzimage when the exp
From: Federico Serafini
MISRA C Rule 14.3 is already tagged as clean: add it to the
monitored set to avoid regressions.
Signed-off-by: Federico Serafini
Signed-off-by: Victor Lira
---
Cc: Andrew Cooper
Cc: Anthony PERARD
Cc: Michal Orzel
Cc: Jan Beulich
Cc: Julien Grall
Cc: Roger Pau Monn
From: Federico Serafini
MISRA C Rule 14.3 states that "Controlling expressions shall not be
invariant".
Add a SAF comment to deviate the rule for build configurations without
CONFIG_LLC_COLORING enabled.
Signed-off-by: Federico Serafini
Signed-off-by: Victor Lira
---
Cc: Andrew Cooper
Cc: An
From: Nicola Vetrini
Rule 19.1 states: "An object shall not be assigned or copied
to an overlapping object". Since the "call" and "compat_call" are
fields of the same union, reading from one member and writing to
the other violates the rule, while not causing Undefined Behavior
due to their relat
From: Nicola Vetrini
Rule 19.1 states: "An object shall not be assigned or copied
to an overlapping object". Since the "call" and "compat_call" are
fields of the same union, reading from one member and writing to
the other violates the rule, while not causing Undefined Behavior
due to their relat
Previously Xen placed the hypercall page at the highest possible MFN,
but this caused problems on systems where there is more than 36 bits
of physical address space.
In general, it also seems unreliable to assume that the highest possible
MFN is not already reserved for some other purpose.
Change
From: Andrei Cherechesu
Normally, the Imagebuilder would precompute the sizes of the loaded
binaries and addresses where they are loaded before generating the
script, and the sizes and addresses that needed to be provided to
Xen via /chosen would be hardcoded in the boot script.
Added an option
On Thu, 3 Apr 2025, dm...@proton.me wrote:
> From: Denis Mukhin
>
> Introduce conring_flush() to ensure all messages kept in the internal
> console ring are sent to all physical consoles (serial, VGA (x86))
> after their initialization is completed.
>
> Resolves: https://gitlab.com/xen-project/x
On Thu, 3 Apr 2025, dm...@proton.me wrote:
> From: Denis Mukhin
>
> guest_console_write() duplicates the code from __putstr(), eliminate code
> duplication.
>
> Introduce console_puts() for writing a buffer to console devices.
>
> Also, introduce internal console flags to control which console
On 25/4/25 16:31, Edgar E. Iglesias wrote:
From: "Edgar E. Iglesias"
Today, we don't track write-abiliy in the cache, if a user
requests a readable mapping followed by a writeable mapping
on the same page, the second lookup will incorrectly hit
the readable entry.
Split mapcache_grants by ro a
On Thu, 3 Apr 2025, dm...@proton.me wrote:
> From: Denis Mukhin
>
> guest_console_write() duplicates the code from __putstr(), eliminate code
> duplication.
>
> Introduce console_puts() for writing a buffer to console devices.
>
> Also, introduce internal console flags to control which console
On 4/24/25 12:10, Alejandro Vallejo wrote:
From: "Daniel P. Smith"
Look for a subnode of type `multiboot,kernel` within a domain node. If
found, locate it using the multiboot module helper to generically ensure
it lives in the module list. If the bootargs property is present and
there was not a
On 4/23/25 15:27, Jason Andryuk wrote:
On 2025-04-19 18:08, Daniel P. Smith wrote:
The bzimage logic uses the unit global orig_image_len to hold the
original
module length for the kernel when the headroom is calculated. It then
uses
orig_image_len to locate the start of the bzimage when the exp
Hi,
> On Apr 25, 2025, at 2:02 PM, Jason Andryuk wrote:
>
> On 2025-04-25 12:51, Ariadne Conill wrote:
>> Previously Xen placed the hypercall page at the highest possible MFN,
>> but this caused problems on systems where there is more than 36 bits
>> of physical address space.
>> In general, it
On 2025-04-25 12:51, Ariadne Conill wrote:
Previously Xen placed the hypercall page at the highest possible MFN,
but this caused problems on systems where there is more than 36 bits
of physical address space.
In general, it also seems unreliable to assume that the highest possible
MFN is not alr
On Thu, 3 Apr 2025, dm...@proton.me wrote:
> From: Denis Mukhin
>
> Move console_locks_busted handling inside conring_puts() to remove
> tasklet code duplication.
>
> Signed-off-by: Denis Mukhin
This patch is a good cleanup but makes one functional change: previously
guest_console_write would
On 4/23/25 15:50, Jason Andryuk wrote:
On 2025-04-19 18:08, Daniel P. Smith wrote:
When constructing domU, and specifically the event channels for their
console
and xenstore event channels, the domid for the backing domain must be
known.
Therefore, the control, hardware, and xenstore domains a
On 4/20/25 05:36, Jürgen Groß wrote:
On 20.04.25 00:07, Daniel P. Smith wrote:
Relocated the function sched_setup_dom0_vcpus(), which was protected
by an
ifdef CONFIG_X86, from common/sched to the hyperlaunch domain builder.
Rename
it to alloc_dom_vcpus() to better reflect the purpose of the f
On 4/25/25 11:22, Alejandro Vallejo wrote:
On Sat Apr 19, 2025 at 11:07 PM BST, Daniel P. Smith wrote:
Convert alloc_dom0_vcpu0() to dom0_set_affinity(), making it only set up the
node affinity based on command line parameters passed. At the same time,
introduce alloc_dom_vcpu0() as the replacem
On 4/22/25 16:36, Jason Andryuk wrote:
On 2025-04-19 18:07, Daniel P. Smith wrote:
The domain configuration may request more vcpus than are present in
the system.
For dom0, the function dom0_max_vcpus() was used to clamp down to
physically
available vcpus. Here we are introducing a generalized
On 25/04/2025 5:51 pm, Ariadne Conill wrote:
> diff --git a/xen/arch/x86/guest/hyperv/hyperv.c
> b/xen/arch/x86/guest/hyperv/hyperv.c
> index 6989af38f1..637b4bf335 100644
> --- a/xen/arch/x86/guest/hyperv/hyperv.c
> +++ b/xen/arch/x86/guest/hyperv/hyperv.c
> @@ -98,10 +97,22 @@ static void __init
On Fri, Apr 25, 2025 at 12:40:40PM -0700, Stefano Stabellini wrote:
> From: Andrei Cherechesu
>
> Normally, the Imagebuilder would precompute the sizes of the loaded
> binaries and addresses where they are loaded before generating the
> script, and the sizes and addresses that needed to be provid
From: Xenia Ragiadakou
Dom0 PVH might need XENMEM_exchange when passing contiguous memory
addresses to firmware or co-processors not behind an IOMMU.
XENMEM_exchange was blocked for HVM/PVH DomUs, and accidentally it
impacted Dom0 PVH as well.
Permit Dom0 PVH to call XENMEM_exchange while leavi
On April 25, 2025 9:13:31 AM PDT, Arnd Bergmann wrote:
>On Fri, Apr 25, 2025, at 17:34, H. Peter Anvin wrote:
>> On April 25, 2025 7:15:15 AM PDT, Arnd Bergmann wrote:
>>
>> I really don't like testing an unrelated feature (CMOV for PAE);
>
>How about a new symbol with the opposite polarity, e.g
On April 25, 2025 5:51:27 AM PDT, "Jürgen Groß" wrote:
>On 25.04.25 14:33, Peter Zijlstra wrote:
>> On Wed, Apr 23, 2025 at 06:05:19PM +0200, Jürgen Groß wrote:
>>
It's not a major change, but when it is patched to use the immediate
form MSR write instruction, it's straightforwardly str
From: Andrei Cherechesu
Normally, the Imagebuilder would precompute the sizes of the loaded
binaries and addresses where they are loaded before generating the
script, and the sizes and addresses that needed to be provided to
Xen via /chosen would be hardcoded in the boot script.
Added an option
On Fri, 25 Apr 2025, Orzel, Michal wrote:
> On 25/04/2025 03:16, Stefano Stabellini wrote:
> > From: Andrei Cherechesu
> >
> > Normally, the Imagebuilder would precompute the sizes of the loaded
> > binaries and addresses where they are loaded before generating the
> > script, and the sizes and a
On 4/22/25 9:02 AM, Jan Beulich wrote:
On 18.04.2025 12:43, Oleksii Kurochko wrote:
On 4/15/25 4:53 PM, Jan Beulich wrote:
On 08.04.2025 17:57, Oleksii Kurochko wrote:
--- a/xen/arch/riscv/imsic.c
+++ b/xen/arch/riscv/imsic.c
@@ -14,12 +14,68 @@
#include
#include
#include
+#includ
On Fri, 25 Apr 2025, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Today, we don't track write-abiliy in the cache, if a user
> requests a readable mapping followed by a writeable mapping
> on the same page, the second lookup will incorrectly hit
> the readable entry.
>
> Split mapcac
On 2025-04-25 10:57, Jan Beulich wrote:
Without doing so we could trigger the ASSERT_UNREACHABLE() in
subpage_mmio_write_emulate(). A comment there actually says this
validation would already have been done ...
Fixes: 8847d6e23f97 ("x86/mm: add API for marking only part of a MMIO page read
only
On 4/15/25 3:45 PM, Jan Beulich wrote:
On 15.04.2025 15:39, Oleksii Kurochko wrote:
On 4/10/25 5:53 PM, Jan Beulich wrote:
On 08.04.2025 17:57, Oleksii Kurochko wrote:
+{
+const __be32 *cell;
+int ac;
+uint32_t len;
+
+ac = dt_n_addr_cells(cpun);
+cell = dt_get_property(cp
Previously Xen placed the hypercall page at the highest possible MFN,
but this caused problems on systems where there is more than 36 bits
of physical address space.
In general, it also seems unreliable to assume that the highest possible
MFN is not already reserved for some other purpose.
Fixes:
On April 25, 2025 5:33:17 AM PDT, Peter Zijlstra wrote:
>On Wed, Apr 23, 2025 at 06:05:19PM +0200, Jürgen Groß wrote:
>
>> > It's not a major change, but when it is patched to use the immediate
>> > form MSR write instruction, it's straightforwardly streamlined.
>>
>> It should be rather easy to
On Fri, Apr 25, 2025, at 17:34, H. Peter Anvin wrote:
> On April 25, 2025 7:15:15 AM PDT, Arnd Bergmann wrote:
>
> I really don't like testing an unrelated feature (CMOV for PAE);
How about a new symbol with the opposite polarity, e.g. CONFIG_CPU_586?
In that case, X86_HAVE_PAE and X86_CMOV coul
On 2025-04-25 10:07, Jan Beulich wrote:
On 24.04.2025 23:45, Stefano Stabellini wrote:
On Thu, 24 Apr 2025, Jan Beulich wrote:
On 23.04.2025 19:54, victorm.l...@amd.com wrote:
From: Nicola Vetrini
MISRA C Rules 21.1 ("#define and #undef shall not be used on a
reserved identifier or reserved
On Fri, 25 Apr 2025, Xin Li (Intel) wrote:
> For some reason, there are some TSC-related functions in the MSR
> header even though there is a tsc.h header.
>
> Relocate rdtsc{,_ordered}() from to , and
> subsequently remove the inclusion of in .
> Consequently, must be included in several sour
On April 25, 2025 7:15:15 AM PDT, Arnd Bergmann wrote:
>From: Arnd Bergmann
>
>With cx8 and tsc being mandatory features, the only important
>architectural features are now cmov and pae.
>
>Change the large list of target CPUs to no longer pick the instruction set
>itself but only the mtune= opti
On Sat Apr 19, 2025 at 11:07 PM BST, Daniel P. Smith wrote:
> Convert alloc_dom0_vcpu0() to dom0_set_affinity(), making it only set up the
> node affinity based on command line parameters passed. At the same time,
> introduce alloc_dom_vcpu0() as the replacement for alloc_dom0_vcpu(). Then
> have
On Thu Apr 24, 2025 at 5:10 PM BST, Alejandro Vallejo wrote:
> From: "Daniel P. Smith"
>
> Introduce the ability to assign capabilities to a domain via its definition in
> device tree. The first capability enabled to select is the control domain
> capability. The capability property is a bitfield
On April 25, 2025 12:01:29 AM PDT, "Jürgen Groß" wrote:
>On 25.04.25 05:44, H. Peter Anvin wrote:
>> On 4/24/25 18:15, H. Peter Anvin wrote:
>>> On 4/24/25 01:14, Jürgen Groß wrote:
>
> Actually, that is how we get this patch with the existing alternatives
> infrastructure. And we to
On Tue Apr 22, 2025 at 9:36 PM BST, Jason Andryuk wrote:
> On 2025-04-19 18:07, Daniel P. Smith wrote:
>> +limit = dom0_max_vcpus();
>
> dom0_max_vcpus() applies Xen's dom0_max_vcpus command line option. That
> is desirable for a traditional dom0. For a disaggregated, Hyperlaunch
> syst
On Fri, Apr 25, 2025 at 12:58:01PM +0100, Alejandro Vallejo wrote:
> On Thu Apr 24, 2025 at 11:19 PM BST, dmkhn wrote:
> > On Thu, Apr 24, 2025 at 05:10:10PM +0100, Alejandro Vallejo wrote:
> >> Hi,
> >>
> >> v4:
> >> https://lore.kernel.org/xen-devel/20250417124844.11143-1-agarc...@amd.com/
> >>
Without doing so we could trigger the ASSERT_UNREACHABLE() in
subpage_mmio_write_emulate(). A comment there actually says this
validation would already have been done ...
Fixes: 8847d6e23f97 ("x86/mm: add API for marking only part of a MMIO page read
only")
Signed-off-by: Jan Beulich
---
v2: Emi
On 25.04.2025 15:48, Andrew Cooper wrote:
> On 25/04/2025 2:13 pm, Jan Beulich wrote:
>> On 25.04.2025 15:05, Andrew Cooper wrote:
>>> On 25/04/2025 1:48 pm, Jan Beulich wrote:
On 25.04.2025 13:24, Andrew Cooper wrote:
> The type used for pagetable attributes/permissions is currently unsig
From: "Edgar E. Iglesias"
This fixes an issue with grant mappings when a read-only
mapping is requested followed by a read-write mapping for
the same page. Today, we don't track write-ability and
read-write lookups hit on read-only entries.
This series is an attempt to fix this by splitting mapc
From: "Edgar E. Iglesias"
Today, we don't track write-abiliy in the cache, if a user
requests a readable mapping followed by a writeable mapping
on the same page, the second lookup will incorrectly hit
the readable entry.
Split mapcache_grants by ro and rw access. Grants will now
have separate w
From: Arnd Bergmann
With cx8 and tsc being mandatory features, the only important
architectural features are now cmov and pae.
Change the large list of target CPUs to no longer pick the instruction set
itself but only the mtune= optimization level and in-kernel optimizations
that remain compatib
On 25/04/2025 15:05, Julien Grall wrote:
Hi Ayan,
Hi Julien,
On 25/04/2025 13:45, Ayan Kumar Halder wrote:
Add the definitions for HPRBAR<0..31>, HPRLAR<0..31> and HPRENR.
The definitions are taken from ARM DDI 0568A.c ID110520, E2.2.3
HPRBAR,
E2.2.4 HPRENR and E2.2.6 HPRLAR.
Introduce p
Hi Ayan,
On 25/04/2025 13:45, Ayan Kumar Halder wrote:
Add the definitions for HPRBAR<0..31>, HPRLAR<0..31> and HPRENR.
The definitions are taken from ARM DDI 0568A.c ID110520, E2.2.3 HPRBAR,
E2.2.4 HPRENR and E2.2.6 HPRLAR.
Introduce pr_t typedef which is a structure having the prbar and prlar
On 25/04/2025 2:13 pm, Jan Beulich wrote:
> On 25.04.2025 15:05, Andrew Cooper wrote:
>> On 25/04/2025 1:48 pm, Jan Beulich wrote:
>>> On 25.04.2025 13:24, Andrew Cooper wrote:
The type used for pagetable attributes/permissions is currently unsigned
int,
but needs to become architec
On Thu, Apr 24, 2025 at 07:51:21PM +0100, Andrew Cooper wrote:
> On 24/04/2025 7:47 pm, Sergii Dmytruk wrote:
> >> Alignment that large is unexpected, and I suspect we want to fix it. Is
> >> it pre-existing, or something introduced by your series?
> >>
> >> ~Andrew
> > Pre-existing one. I can se
Hi Ayan
On 25/04/2025 13:00, Ayan Kumar Halder wrote:
+ unsigned int ns:1; /* Reserved 0 by hardware */
+ unsigned int res0:1; /* Reserved 0 by hardware */
Then, we can change this on Arm32 as well.
+ unsigned int limit:26; /* Limit Address */
NIT: Can we align th
Hi Mark,
On 18/04/2025 16:00, Mark Brown wrote:
Hello all,
This is my first post to xen-devel. Since I'm new, let me give a brief intro about
"Why?"
Welcome :)
1. I am interested in easing the ongoing burden of repeatedly obtaining safety
certification for Xen for eventual use in high assura
On 25.04.2025 15:05, Andrew Cooper wrote:
> On 25/04/2025 1:48 pm, Jan Beulich wrote:
>> On 25.04.2025 13:24, Andrew Cooper wrote:
>>> The type used for pagetable attributes/permissions is currently unsigned
>>> int,
>>> but needs to become architecture dependent as PPC needs unsigned long.
>>>
>>
On 25/04/2025 1:48 pm, Jan Beulich wrote:
> On 25.04.2025 13:24, Andrew Cooper wrote:
>> The type used for pagetable attributes/permissions is currently unsigned int,
>> but needs to become architecture dependent as PPC needs unsigned long.
>>
>> Introduce mm-types.h to house pte_attr_t.
>>
>> Give
On 25.04.2025 13:29, Oleksii Kurochko wrote:
>
> On 4/25/25 1:24 PM, Andrew Cooper wrote:
>> The type used for pagetable attributes/permissions is currently unsigned int,
>> but needs to become architecture dependent as PPC needs unsigned long.
>
> Not only PPC, RISC-V needs it too.
>
>>
>> Intr
On Fri, Apr 25, 2025 at 01:36:42PM +0100, Alejandro Vallejo wrote:
> On Wed Apr 23, 2025 at 12:32 PM BST, Roger Pau Monne wrote:
> > There are several errata on Intel regarding the usage of the MONITOR/MWAIT
> > instructions, all having in common that stores to the monitored region
> > might not wa
On Fri Apr 25, 2025 at 1:44 PM BST, Roger Pau Monné wrote:
> On Fri, Apr 25, 2025 at 01:23:30PM +0100, Alejandro Vallejo wrote:
>> On Thu Apr 24, 2025 at 1:58 PM BST, Roger Pau Monne wrote:
>> > The commit that added support for retrieving the APIC IDs from the APs
>> > introduced several usages of
On Fri, Apr 25, 2025 at 01:34:23AM -0700, Xin Li (Intel) wrote:
> This patch set is the first part of the patch set:
>
> MSR refactor with new MSR instructions support
>
> @
> https://lore.kernel.org/lkml/20250422082216.1954310-1-...@zytor.com/T/#m5a34be7d4ed55f0baca965cb65452a08e9ad7c8a
>
>
Add the definitions for HPRBAR<0..31>, HPRLAR<0..31> and HPRENR.
The definitions are taken from ARM DDI 0568A.c ID110520, E2.2.3 HPRBAR,
E2.2.4 HPRENR and E2.2.6 HPRLAR.
Introduce pr_t typedef which is a structure having the prbar and prlar members,
each being structured as the registers of the AA
On 25.04.25 14:33, Peter Zijlstra wrote:
On Wed, Apr 23, 2025 at 06:05:19PM +0200, Jürgen Groß wrote:
It's not a major change, but when it is patched to use the immediate
form MSR write instruction, it's straightforwardly streamlined.
It should be rather easy to switch the current wrmsr/rdmsr
On 25/04/2025 1:45 pm, Jan Beulich wrote:
> On 25.04.2025 13:29, Oleksii Kurochko wrote:
>> On 4/25/25 1:24 PM, Andrew Cooper wrote:
>>> The type used for pagetable attributes/permissions is currently unsigned
>>> int,
>>> but needs to become architecture dependent as PPC needs unsigned long.
>> N
On 25.04.2025 13:24, Andrew Cooper wrote:
> The type used for pagetable attributes/permissions is currently unsigned int,
> but needs to become architecture dependent as PPC needs unsigned long.
>
> Introduce mm-types.h to house pte_attr_t.
>
> Given the new toolchain baseline, we can use __has_i
On Fri, Apr 25, 2025 at 01:23:30PM +0100, Alejandro Vallejo wrote:
> On Thu Apr 24, 2025 at 1:58 PM BST, Roger Pau Monne wrote:
> > The commit that added support for retrieving the APIC IDs from the APs
> > introduced several usages of cpuid() with NULL parameters, which is not
> > handled by the u
On 25/04/2025 1:36 pm, Alejandro Vallejo wrote:
> On Wed Apr 23, 2025 at 12:32 PM BST, Roger Pau Monne wrote:
>> There are several errata on Intel regarding the usage of the MONITOR/MWAIT
>> instructions, all having in common that stores to the monitored region
>> might not wake up the CPU.
>>
>> F
On Thu Apr 24, 2025 at 6:41 PM BST, Jason Andryuk wrote:
> On 2025-04-24 12:10, Alejandro Vallejo wrote:
>> From: "Daniel P. Smith"
>>
>> Introduce the ability to specify the desired domain id for the domain
>> definition. The domain id will be populated in the domid property of the
>> domain nod
On Thu Apr 24, 2025 at 5:54 PM BST, Jason Andryuk wrote:
> On 2025-04-24 12:10, Alejandro Vallejo wrote:
>> From: "Daniel P. Smith"
>>
>> Hyperlaunch domain builder will be the consolidated boot time domain
>> building logic framework. Introduces the config option to enable this
>
> "Introduce th
On Wed Apr 23, 2025 at 12:32 PM BST, Roger Pau Monne wrote:
> There are several errata on Intel regarding the usage of the MONITOR/MWAIT
> instructions, all having in common that stores to the monitored region
> might not wake up the CPU.
>
> Fix them by forcing the sending of an IPI for the affect
On Wed, Apr 23, 2025 at 06:05:19PM +0200, Jürgen Groß wrote:
> > It's not a major change, but when it is patched to use the immediate
> > form MSR write instruction, it's straightforwardly streamlined.
>
> It should be rather easy to switch the current wrmsr/rdmsr paravirt patching
> locations to
On Thu Apr 24, 2025 at 1:58 PM BST, Roger Pau Monne wrote:
> The commit that added support for retrieving the APIC IDs from the APs
> introduced several usages of cpuid() with NULL parameters, which is not
> handled by the underlying implementation. For GCC I expect this results in
> writes to the
Hi Julien,
cc-ed Luca for feedback on specific points.
On 18/04/2025 05:54, Julien Grall wrote:
Hi Ayan,
On 18/04/2025 00:55, Ayan Kumar Halder wrote:
Add the definitions for HPRBAR<0..31>, HPRLAR<0..31> and HPRENR.
The definitions are taken from ARM DDI 0568A.c ID110520, E2.2.3
HPRBAR,
E2.
On Thu Apr 24, 2025 at 11:19 PM BST, dmkhn wrote:
> On Thu, Apr 24, 2025 at 05:10:10PM +0100, Alejandro Vallejo wrote:
>> Hi,
>>
>> v4:
>> https://lore.kernel.org/xen-devel/20250417124844.11143-1-agarc...@amd.com/
>> v3:
>> https://lore.kernel.org/xen-devel/20250408160802.49870-1-agarc...@amd.co
On 25/04/2025 12:37 pm, Oleksii Kurochko wrote:
>
>
> On 4/25/25 1:24 PM, Andrew Cooper wrote:
>> From: Shawn Anastasio
>>
>> Signed-off-by: Shawn Anastasio
>> ---
>> CC: Jan Beulich
>> CC: Roger Pau Monné
>> CC: Stefano Stabellini
>> CC: Julien Grall
>> CC: Volodymyr Babchuk
>> CC: Bertrand
On 4/25/25 1:24 PM, Andrew Cooper wrote:
From: Shawn Anastasio
Signed-off-by: Shawn Anastasio
---
CC: Jan Beulich
CC: Roger Pau Monné
CC: Stefano Stabellini
CC: Julien Grall
CC: Volodymyr Babchuk
CC: Bertrand Marquis
CC: Michal Orzel
CC: Oleksii Kurochko
CC: Shawn Anastasio
Possibly not for ta
On 25/04/2025 12:32 pm, Roger Pau Monne wrote:
> There's an off-by-one when calculating the last byte in the input array to
> bitmap_to_xenctl_bitmap(), which leads to bitmaps with sizes multiple of 8
> to over-read and incorrectly use a byte past the end of the array.
>
> Fixes: 288c4641c80d ('xen
On 4/25/25 1:24 PM, Andrew Cooper wrote:
From: Shawn Anastasio
Several APIs take an architecture-dependent set of flags in an unsigned int,
but this needs to be a wider type to support PPC.
The new type pte_attr_t has been introduced for this purpose, so switch to it
in map_pages_to_xen(), __v
There's an off-by-one when calculating the last byte in the input array to
bitmap_to_xenctl_bitmap(), which leads to bitmaps with sizes multiple of 8
to over-read and incorrectly use a byte past the end of the array.
Fixes: 288c4641c80d ('xen: simplify bitmap_to_xenctl_bitmap for little endian')
S
On 4/25/25 1:24 PM, Andrew Cooper wrote:
The type used for pagetable attributes/permissions is currently unsigned int,
but needs to become architecture dependent as PPC needs unsigned long.
Not only PPC, RISC-V needs it too.
Introduce mm-types.h to house pte_attr_t.
Do we really want a se
From: Shawn Anastasio
Signed-off-by: Shawn Anastasio
---
CC: Jan Beulich
CC: Roger Pau Monné
CC: Stefano Stabellini
CC: Julien Grall
CC: Volodymyr Babchuk
CC: Bertrand Marquis
CC: Michal Orzel
CC: Oleksii Kurochko
CC: Shawn Anastasio
Possibly not for taking on it's own (might be better
The type used for pagetable attributes/permissions is currently unsigned int,
but needs to become architecture dependent as PPC needs unsigned long.
Introduce mm-types.h to house pte_attr_t.
Given the new toolchain baseline, we can use __has_include() now to remove the
need for boilerplate on mos
From: Shawn Anastasio
Several APIs take an architecture-dependent set of flags in an unsigned int,
but this needs to be a wider type to support PPC.
The new type pte_attr_t has been introduced for this purpose, so switch to it
in map_pages_to_xen(), __vmap() and modify_xen_mappings{,_lite}().
N
This is in order to support PPC needing wider flags, but I've also written it
as a showcase of the new __has_include().
https://gitlab.com/xen-project/hardware/xen-staging/-/pipelines/1786141700
Andrew Cooper (1):
xen/mm: Introduce mm-types.h
Shawn Anastasio (2):
xen/mm: Switch some APIs ove
On 3/10/25 10:22 AM, Oleksii Kurochko wrote:
On 3/6/25 7:25 PM, Shawn Anastasio wrote:
Xen's memory management APIs map_pages_to_xen, modify_xen_mappings,
set_fixmap, ioremap_attr, and __vmap all use an unsigned int to
represent architecture-dependent page table entry flags. This assumption
i
On Fri, Apr 25, 2025 at 11:19:21AM +0200, Jan Beulich wrote:
> On 25.04.2025 11:02, Roger Pau Monné wrote:
> > On Thu, Apr 24, 2025 at 02:38:29PM -0700, Lira, Victor M wrote:
> >> Hello all,
> >>
> >> Here is the output from Roger's patch.
> >> This is the section of interest:
> >>
> >>> (XEN) [ 7.
On 25.04.25 10:34, Xin Li (Intel) wrote:
As pmu_msr_{read,write}() are now wrappers of pmu_msr_chk_emulated(),
remove them and use pmu_msr_chk_emulated() directly.
As pmu_msr_chk_emulated() could easily return false in the cases where
it would set *emul to false, remove the "emul" argument and u
On 25.04.25 10:34, Xin Li (Intel) wrote:
hpa found that pmu_msr_write() is actually a completely pointless
function [1]: all it does is shuffle some arguments, then calls
pmu_msr_chk_emulated() and if it returns true AND the emulated flag
is clear then does *exactly the same thing* that the calli
On Tue, Apr 08, 2025 at 12:38:16PM +0200, Jan Beulich wrote:
> On 30.03.2025 18:03, Hongbo wrote:
> > +{
> > +char *path_dup = libxl__strdup(gc, path_env);
> > +char *saveptr;
> > +
> > +char *path = strtok_r(path_dup, ":",
On 24.04.2025 12:05, Fabian Specht wrote:
> On Thu, Apr 24, 2025 at 08:34:42AM +0200, Jan Beulich wrote:
>> Since ...
>>
>>> Similar code resides in the same file in lines 87, 125 and 127.
>>
>> ... all of these are shifts by 16, could you clarify what it is that you
>> want to shift by 4? Imo what
On 25.04.2025 11:02, Roger Pau Monné wrote:
> On Thu, Apr 24, 2025 at 02:38:29PM -0700, Lira, Victor M wrote:
>> Hello all,
>>
>> Here is the output from Roger's patch.
>> This is the section of interest:
>>
>>> (XEN) [ 7.547326] d0 has maximum 3328PIRQs
>>> (XEN) [ 7.555644] *** Building a PVH Dom
On 24.04.2025 14:45, Alejandro Vallejo wrote:
> Xen nowadays crashes under some Hyper-V configurations when
> paddr_bits>36. At the 44bit boundary we reach an edge case in which the
> end of the guest physical address space is not representable using 32bit
> MFNs. Furthermore, it's an act of faith
On 25.04.2025 11:04, Roger Pau Monné wrote:
> On Fri, Apr 25, 2025 at 10:54:36AM +0200, Jan Beulich wrote:
>> On 24.04.2025 15:04, Roger Pau Monné wrote:
>>> On Thu, Apr 24, 2025 at 12:41:43PM +0100, Andrew Cooper wrote:
On 24/04/2025 11:38 am, Roger Pau Monne wrote:
> There's an off-by-on
On 24.04.2025 16:04, Andrew Cooper wrote:
> I have a sneaking suspicion that this is sufficient:
>
> diff --git a/xen/arch/x86/x86_emulate/private.h
> b/xen/arch/x86/x86_emulate/private.h
> index 30be59547032..9f3d6f0e5357 100644
> --- a/xen/arch/x86/x86_emulate/private.h
> +++ b/xen/arch/x86/x86_
On Fri, Apr 25, 2025 at 10:54:36AM +0200, Jan Beulich wrote:
> On 24.04.2025 15:04, Roger Pau Monné wrote:
> > On Thu, Apr 24, 2025 at 12:41:43PM +0100, Andrew Cooper wrote:
> >> On 24/04/2025 11:38 am, Roger Pau Monne wrote:
> >>> There's an off-by-one when calculating the last byte in the input a
On Thu, Apr 24, 2025 at 02:38:29PM -0700, Lira, Victor M wrote:
> Hello all,
>
> Here is the output from Roger's patch.
> This is the section of interest:
>
> > (XEN) [ 7.547326] d0 has maximum 3328PIRQs
> > (XEN) [ 7.555644] *** Building a PVH Dom0 ***
> > (XEN) [ 7.567780] d0: identity mappings
On 24.04.2025 15:04, Roger Pau Monné wrote:
> On Thu, Apr 24, 2025 at 12:41:43PM +0100, Andrew Cooper wrote:
>> On 24/04/2025 11:38 am, Roger Pau Monne wrote:
>>> There's an off-by-one when calculating the last byte in the input array to
>>> bitmap_to_xenctl_bitmap(), which leads to bitmaps with si
As pmu_msr_{read,write}() are now wrappers of pmu_msr_chk_emulated(),
remove them and use pmu_msr_chk_emulated() directly.
As pmu_msr_chk_emulated() could easily return false in the cases where
it would set *emul to false, remove the "emul" argument and use the
return value instead.
While at it,
For some reason, there are some TSC-related functions in the MSR
header even though there is a tsc.h header.
Relocate rdtsc{,_ordered}() from to , and
subsequently remove the inclusion of in .
Consequently, must be included in several source files
that previously did not require it.
Signed-off
On Thu, Apr 24, 2025 at 05:23:26PM -0400, Jason Andryuk wrote:
> The format string lacks a space, so mfn and type run together:
> (XEN) d0v0 :06:00.7: existing mapping (mfn: 753037type: 0) at 0x1
> clobbers MSIX MMIO area
>
> Add a space. Additionally, move the format string to a single long
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