Re: Arm: AArch32: Need suggestions to support 32 bit physical addresses

On Wed, 30 Nov 2022 15:39:56 + Ayan Kumar Halder wrote: Hi Ayan, > On 30/11/2022 13:13, Andre Przywara wrote: > > On Wed, 30 Nov 2022 08:09:53 +0100 > > Jan Beulich wrote: > > > > Hi Ayan, > Hi Andre, > > > >> On 29.11.2022 19:18, Ayan Ku

Re: Arm: AArch32: Need suggestions to support 32 bit physical addresses

On Wed, 30 Nov 2022 08:09:53 +0100 Jan Beulich wrote: Hi Ayan, > On 29.11.2022 19:18, Ayan Kumar Halder wrote: > > On 29/11/2022 15:52, Julien Grall wrote: > >> On 29/11/2022 16:23, Ayan Kumar Halder wrote: > >>> On 29/11/2022 14:52, Julien Grall wrote: > On 29/11/2022 14:57, Ayan

Re: Xen Arm vpl011 UART will cause segmentation fault in Linux guest

On Thu, 10 Nov 2022 12:32:49 -0800 (PST) Stefano Stabellini wrote: Hi, > On Wed, 9 Nov 2022, Michal Orzel wrote: > > Hi Jiamei, > > > > On 09/11/2022 09:25, Jiamei Xie wrote: > > > > > > > > > Hi Michal， > > > > > > Below log can be got when stating the linux guest. It says 9c09 is sbsa.

Re: GICv3: Aarch32: Need guidance on the atomic access of "union host_lpi" or if ITS is supported on R52

On Fri, 28 Oct 2022 12:44:08 +0100 Ayan Kumar Halder wrote: > On 27/10/2022 15:36, Andre Przywara wrote: > > On Thu, 27 Oct 2022 14:38:52 +0100 > > Ayan Kumar Halder wrote: > > > > Hi Ayan, > Hi Andre / Julien, > > > >> On 25/10/2022 14:55, Andr

Re: [XEN v5] xen/arm: vGICv3: Emulate properly 32-bit access on GICR_PENDBASER

9ce4 ("ARM: vGICv3: handle virtual LPI pending and > property tables") > Signed-off-by: Ayan Kumar Halder > Release-acked-by: Henry Wang Reviewed-by: Andre Przywara Cheers, Andre > --- > > Changes from:- > > v1 - 1. Extracted this fix from "[RFC PA

Re: [XEN v1] xen/arm: vGICv3: Restore the interrupt state correctly

to restore the saved interrupt state. > > Fixes: fe7fa1332dabd9ce4 ("ARM: vGICv3: handle virtual LPI pending and > property tables") > Signed-off-by: Ayan Kumar Halder Thanks for fixing this! Reviewed-by: Andre Przywara Cheers, Andre > --- > xen/arch/arm/vgic-v3.c | 2 +- > 1

Re: [XEN v4] xen/arm: vGICv3: Emulate properly 32-bit access on GICR_PENDBASER

On Thu, 27 Oct 2022 16:40:01 +0100 Ayan Kumar Halder wrote: Hi Ayan, > On 27/10/2022 10:44, Andre Przywara wrote: > > On Wed, 26 Oct 2022 19:30:04 +0100 > > Ayan Kumar Halder wrote: > > > > Hi, > > Hi Andre, > > I need a clarification. > >

Re: GICv3: Aarch32: Need guidance on the atomic access of "union host_lpi" or if ITS is supported on R52

On Thu, 27 Oct 2022 14:38:52 +0100 Ayan Kumar Halder wrote: Hi Ayan, > On 25/10/2022 14:55, Andre Przywara wrote: > > On Tue, 25 Oct 2022 13:25:52 +0100 > > Ayan Kumar Halder wrote: > > > > Hi, > > Hi Andre, > > Many thanks for the explanation. &

Re: [XEN v4] xen/arm: vGICv3: Emulate properly 32-bit access on GICR_PENDBASER

On Wed, 26 Oct 2022 19:30:04 +0100 Ayan Kumar Halder wrote: Hi, > If a guest is running in 32 bit mode and it tries to access > "GICR_PENDBASER + 4" mmio reg, it will be trapped to Xen. vreg_reg64_extract() > will return the value stored "v->arch.vgic.rdist_pendbase + 4". > This will be stored

Re: GICv3: Aarch32: Need guidance on the atomic access of "union host_lpi" or if ITS is supported on R52

On Tue, 25 Oct 2022 13:25:52 +0100 Ayan Kumar Halder wrote: Hi, > Hi Andre/All, > > This came up while porting Xen on R52. > > Refer "ARM DDI 0568A.cID110520", B1.3.1 > > "A Generic Interrupt Controller (GIC) implemented with an Armv8-R PE > must not implement LPI support. " > > Does this

Re: [XEN v2] GICv3: Emulate GICR_PENDBASER correctly for 32 bit guests

dabd9ce4 ("ARM: vGICv3: handle virtual LPI pending and > property tables") > Signed-off-by: Ayan Kumar Halder Indeed, the patch looks good to me. Also checked the other users of vreg_reg64_extract(), they seem to be all correct, by first building the value, then running the extract

Re: Need guidance regarding emulation of GICR_PENDBASER and GICR_PROPBASER registers on Aarch32

ould need to change the guest to not do so. See above what Linux does: always access them in two chunks, so it works everywhere. Cheers, Andre > However, looking at the following commit in kernel, I am a bit confused. > > commit 0aa1de57319c4e023187aca0d59dd593a96459a8 > Author: An

Re: [XEN v3] xen/arm64: io: Decode ldr/str post-indexing instructions

On Mon, 24 Jan 2022 17:58:55 + Julien Grall wrote: Hi Julien, > Hi Andre, > > On 24/01/2022 14:36, Andre Przywara wrote: > > On Mon, 24 Jan 2022 12:07:42 + > >> Also, if an instruction is being modified by the guest (after it has > >> been loaded

Re: [XEN v3] xen/arm64: io: Decode ldr/str post-indexing instructions

On Mon, 24 Jan 2022 12:07:42 + Ayan Kumar Halder wrote: Hi Ayan, > Many thanks for your feedback. I have one clarification :- > > On 22/01/2022 01:30, Andre Przywara wrote: > > On Thu, 20 Jan 2022 21:55:27 + > > Ayan Kumar Halder wrote: > > > >

Re: [XEN v3] xen/arm64: io: Decode ldr/str post-indexing instructions

On Thu, 20 Jan 2022 21:55:27 + Ayan Kumar Halder wrote: Hi, > At the moment, Xen is only handling data abort with valid syndrome (i.e. > ISV=0). Unfortunately, this doesn't cover all the instructions a domain > could use to access MMIO regions. > > For instance, a baremetal OS can use any

Re: [XEN v2] xen/arm64: io: Decode 32-bit ldr/str post-indexing instructions

On Mon, 10 Jan 2022 14:33:11 + Ayan Kumar Halder wrote: Hi Ayan, > Many thanks for your inputs. It is making better sense now. Much > appreciated. > > A few questions/clarifications :- > > On 06/01/2022 15:33, Andre Przywara wrote: > > On Wed, 5 Jan 2022 16:55

Re: [XEN v2] xen/arm64: io: Decode 32-bit ldr/str post-indexing instructions

On Wed, 5 Jan 2022 16:55:11 + Ayan Kumar Halder wrote: Hi, > Thank you so much for your feedback. > > I need a couple of clarifications before I can start with the v3 patch. > > On 08/12/2021 12:00, Andre Przywara wrote: > > On Mon, 6 Dec 2021 19:31:06 + &g

Re: [XEN v2] xen/arm64: io: Decode 32-bit ldr/str post-indexing instructions

nks for your comments. They are useful. > >> > >> On 30/11/2021 09:49, Andre Przywara wrote: > >>> On Mon, 29 Nov 2021 19:16:38 + > >>> Ayan Kumar Halder wrote: > >>> Hi, > >>>> At the moment, Xen is only handling data abor

Re: [XEN v2] xen/arm64: io: Decode 32-bit ldr/str post-indexing instructions

On Tue, 30 Nov 2021 19:13:41 + Ayan Kumar Halder wrote: Hi Ayan, > Thanks for your comments. They are useful. > > On 30/11/2021 09:49, Andre Przywara wrote: > > On Mon, 29 Nov 2021 19:16:38 + > > Ayan Kumar Halder wrote: > > > > Hi, > > &

Re: [XEN v2] xen/arm64: io: Decode 32-bit ldr/str post-indexing instructions

On Wed, 1 Dec 2021 08:41:13 + Bertrand Marquis wrote: Hi, > > On 30 Nov 2021, at 19:13, Ayan Kumar Halder > > wrote: > > > > Hi Andre, > > > > Thanks for your comments. They are useful. > > > > On 30/11/2021 09:49, Andre Przywara wrote: &

Re: [XEN v2] xen/arm64: io: Decode 32-bit ldr/str post-indexing instructions

On Mon, 29 Nov 2021 19:16:38 + Ayan Kumar Halder wrote: Hi, > At the moment, Xen is only handling data abort with valid syndrome (i.e. > ISV=0). Unfortunately, this doesn't cover all the instructions a domain > could use to access MMIO regions. > > For instance, Xilinx baremetal OS will

Re: [RFC PATCH] Added the logic to decode 32 bit ldr/str post-indexing instructions

On Fri, 26 Nov 2021 15:28:06 + Ayan Kumar Halder wrote: Hi Ayan, > Many thanks for your inputs. > Apologies if I sound dumb, but I need a few clarifications. > > On 26/11/2021 13:14, Andre Przywara wrote: > > On Fri, 19 Nov 2021 16:52:02 + > > Ayan Kumar Ha

Re: [RFC PATCH] Added the logic to decode 32 bit ldr/str post-indexing instructions

On Fri, 19 Nov 2021 16:52:02 + Ayan Kumar Halder wrote: Hi, > At present, post indexing instructions are not emulated by Xen. > When Xen gets the exception, EL2_ESR.ISV bit not set. Thus as a > result, data abort is triggered. > > Added the logic to decode ldr/str post indexing

Re: [Kvmtool] Some thoughts on using kvmtool Virtio for Xen

On Tue, 15 Jun 2021 07:12:08 +0100 Wei Chen wrote: Hi Wei, > I have some thoughts of using kvmtool Virtio implementation > for Xen. I copied my markdown file to this email. If you have > time, could you please help me review it? > > Any feedback is welcome! > > # Some thoughts on using

Re: [Xen-devel] [PATCH] xen/arm: Basic support for sunxi/sun50i h6 platform.

On Tue, 3 Dec 2019 16:52:45 + Julien Grall wrote: Hi, > On 03/12/2019 14:38, Andre Przywara wrote: > > On Tue, 3 Dec 2019 11:39:58 + > > Julien Grall wrote: > > > > Hi, > > > >> (+Andre) > >> > >> Hi, > >> >

Re: [Xen-devel] [PATCH] xen/arm: Basic support for sunxi/sun50i h6 platform.

ged the memory map, they missed the opportunity to put each device at least in their own 4K page. Reviewed-by: Andre Przywara If you can wait till this evening, I can even test it. It's actually a shame that we need this enumeration, when all we are after is an answer to the question: Does a device

Re: [Xen-devel] [PATCH] arch: arm: vgic-v3: fix GICD_ISACTIVER range

On Mon, 11 Nov 2019 11:01:07 -0800 (PST) Stefano Stabellini wrote: Hi, > On Sat, 9 Nov 2019, Julien Grall wrote: > > On Sat, 9 Nov 2019, 04:27 Stefano Stabellini, > > wrote: > > On Thu, 7 Nov 2019, Peng Fan wrote: > > > The end should be GICD_ISACTIVERN not GICD_ISACTIVER. > >

Re: [Xen-devel] [PATCH v2 0/2] Raspberry Pi 4 support

On Mon, 29 Jul 2019 09:19:18 -0400 Stewart Hildebrand wrote: Hi, > This is a series to enable UART console for Raspberry Pi 4. Note that I'm > relying on the firmware to initialize the UART (i.e. enable_uart=1 in > config.txt), since full UART initialization on this platform requires >

Re: [Xen-devel] [RFC 5/6] arm64: call enter_hypervisor_head only when it is needed

On Wed, 31 Jul 2019 12:02:20 +0100 Julien Grall wrote: Hi, > On 30/07/2019 18:35, Andrii Anisov wrote: > > > > On 26.07.19 13:59, Julien Grall wrote: > >> Hi, > >> > >> On 26/07/2019 11:37, Andrii Anisov wrote: > >>> From: Andrii Anisov > >>> > >>> On ARM64 we know exactly if trap

Re: [Xen-devel] [PATCH v2 1/2] ns16550: Add compatible string for Raspberry Pi 4

8250/16550 driver for the aux UART [2]. > > Unfortunately the brcm,bcm2835-aux-uart device tree binding doesn't > have the reg-shift and reg-io-width properties [3]. Thus, the reg-shift > and reg-io-width properties are inherent properties of this UART. > > Thanks to Andre Przywara fo

Re: [Xen-devel] [PATCH 2/2] ns16550: Add compatible string for Raspberry Pi 4

On Wed, 24 Jul 2019 14:34:55 + Stewart Hildebrand wrote: Hi, I am afraid this is not enough. In your repo you hack the DT to contain the reg-shift and io-width properties, but those are not part of the "brcm,bcm2835-aux-uart" binding. Using 32-bit accesses is an integral property of this

Re: [Xen-devel] [PATCH v2] gic: drop interrupts enabling on interrupts processing

On Fri, 31 May 2019 18:16:52 +0100 Julien Grall wrote: > Hi, > > On 30/05/2019 17:14, Andrii Anisov wrote: > > > > > > On 29.05.19 18:32, Julien Grall wrote: > >>> BTW, do you hear about plans for the new vgic? Some time ago it was said > >>> that > >>> new vgic implementation going to

Re: [Xen-devel] [PATCH] xen/arm: Black list everything with a PPI

On Thu, 16 May 2019 17:15:36 +0530 Amit Tomer wrote: Hi, > Thanks for having a look at it. > > On Thu, May 16, 2019 at 12:25 AM Oleksandr wrote: > > > > > > On 03.05.19 20:02, Amit Singh Tomar wrote: > > > > Hi, Amit > > > > > XEN should not forward PPIs to Dom0 as it only support SPIs. > >

Re: [Xen-devel] [PATCH] xen/arm: Blacklist PMU with "arm, cortex-a53-pmu"

On Mon, 15 Apr 2019 13:41:41 +0530 Amit Tomer wrote: > Hello, > > > After talking via IRC, the problem is PPIs, that this platform uses for > > PMU interrupts. When Xen tries to setup the IRQ forwarding for Dom0 for > > this device, it fails because it only supports forwarding SPIs. > > So

Re: [Xen-devel] [PATCH v2 for-4.12] gic-vgic: fix an assert condition

> disconnection on debug builds. > > Fixes: ec2a2f1 ("ARM: VGIC: factor out vgic_connect_hw_irq()") > Signed-off-by: Andrii Anisov > Suggested-by: Stefan Nuernberger Reviewed-by: Andre Przywara Cheers, Andre. > --- > in v2: > - updated condition as suggeste

Re: [Xen-devel] [RFC 10/16] gic:vgic:gic-vgic: introduce non-atomic bitops

On Mon, 3 Dec 2018 14:33:08 +0200 Andrii Anisov wrote: Hi Andrii, > On 29.11.18 14:14, Andre Przywara wrote: > > Nah, please don't do this. > Sorry for making you crying looking at this code. > It's terrible, I know. It's rather an idea. > > > Can you

Re: [Xen-devel] [PATCH 1/4] xen/arm: gic: Ensure we have an ISB between ack and do_IRQ()

On 30/11/2018 19:52, Andrii Anisov wrote: > Hello Andre, > > Please see my comments below: > > On 23.11.18 14:18, Andre Przywara wrote: >> Fundamentally there is a semantic difference between edge and level >> triggered IRQs: When the guest has handled an *edge* IRQ

Re: [Xen-devel] [RFC 10/16] gic:vgic:gic-vgic: introduce non-atomic bitops

On Wed, 28 Nov 2018 23:32:05 +0200 Andrii Anisov wrote: Hi, > From: Andrii Anisov > > All bit operations for gic, vgic and gic-vgic are performed under > spinlocks, so there is no need for atomic bit ops here, they only > introduce excessive call to functions used more expensive exclusive >

Re: [Xen-devel] [RFC 02/16] hack: drop GIC v3 support

On Wed, 28 Nov 2018 23:31:57 +0200 Andrii Anisov wrote: Hi, > From: Andrii Anisov > > This reduces some code and conditions in an IRQ processing path, > and opens way to further code reduction. While I understand that this is some sort of a hack, I am commenting just on this patch to

Re: [Xen-devel] [RFC 00/16] Old GIC (gic-vgic) optimizations for GICV2

On Thu, 29 Nov 2018 07:40:00 + Andrii Anisov wrote: > Hello, > > Again, I sent this cover letter only to myself. So, here it is, hope > it does not break the thread. Sorry for the mess. > > > From: Andrii Anisov > Sent: Wednesday, November 28, 2018 11:31 PM > Cc: Andrii Anisov > Subject:

Re: [Xen-devel] [PATCH 1/4] xen/arm: gic: Ensure we have an ISB between ack and do_IRQ()

On Fri, 23 Nov 2018 12:09:41 +0200 Andrii Anisov wrote: Hi, > On 22.11.18 19:22, Julien Grall wrote: > > My biggest worry is you are doing optimization on a vGIC that is > > not fully compliant with how a GIC should behave (e.g edge vs > > level) and with very fragile locking. > Yep, old VGIC

Re: [Xen-devel] [PATCH 1/4] xen/arm: gic: Ensure we have an ISB between ack and do_IRQ()

On Thu, 22 Nov 2018 18:51:13 +0200 Andrii Anisov wrote: Hi, > On 20.11.18 20:47, Julien Grall wrote: > > > > > > On 20/11/2018 18:10, Andrii Anisov wrote: > >> Hello Julien, > >> > >> > >> On 19.11.18 18:42, Julien Grall wrote: > >>> There are no issue about processing IRQs before the

Re: [Xen-devel] Xen boot failure on QEMU (WAS: Re: [PATCH v3] xen:arm: Populate arm64 image header)

On Tue, 9 Oct 2018 09:58:14 +0100 Peter Maydell wrote: Hi, > On 8 October 2018 at 19:00, Julien Grall wrote: > > Per the Linux arm64 booting protocol [1], the load offset can > > definitely be 0. The bootloader (here QEMU) should not assume a > > specific text offset, Linux actually provides

Re: [Xen-devel] [PATCH v3] xen:arm: Populate arm64 image header

aligned address without to worry about relocation. > For instance, it fixes the XEN boot on Amlogic SoC where bootloader(U-BOOT) > always relocates the XEN image to an address range reserved for firmware data. > > Signed-off-by: Amit Singh Tomar Thanks, looks good to me now: Reviewed-

Re: [Xen-devel] [PATCH v2] xen:arm: Populate arm64 image header

Hi, On 05/09/18 13:52, Amit Tomer wrote: > Hello, > > Thanks for having a look. > > On Wed, Sep 5, 2018 at 6:07 PM Andre Przywara wrote: >> >> Hi, >> >> I don't think it's helpful to hide that KERNEL_SIZE definition in >> another file. Please just p

Re: [Xen-devel] [PATCH v2] xen:arm: Populate arm64 image header

Hi, On 04/09/18 18:25, Amit Singh Tomar wrote: > This patch adds image size and flags to XEN image header. It uses > those fields according to the updated Linux kernel image definition. > > With this patch bootloader can now place XEN image anywhere in system > RAM at 2MB aligned address without

Re: [Xen-devel] [PATCH v2] drm/xen-front: fix pointer casts

Hi, On 25/05/18 06:32, Oleksandr Andrushchenko wrote: > On 05/23/2018 02:46 PM, Juergen Gross wrote: >> On 23/05/18 13:36, Oleksandr Andrushchenko wrote: >>> From: Oleksandr Andrushchenko >>> >>> Building for a 32-bit target results in warnings from casting >>> between a 32-bit pointer and a

Re: [Xen-devel] [PATCH] xen: char: Remove unnecessary (uart->irq > 0) check

Hi, On 28/04/18 10:08, Amit Singh Tomar wrote: > While working on MVEBU uart driver, Julien pointed out that (uart->irq > 0) > check is unnecessary during irq set up.if ever there is an invalid irq, driver > initialization itself would be bailed out from platform_get_irq. > > This patch would

Re: [Xen-devel] [PATCH v4] xen/arm: Add MVEBU UART driver for Marvell Armada 3700 SoC

/linux/blob/master/drivers/tty/serial/mvebu-uart.c > commit-id: c685af1108d7c303f0b901413405d68eaeac4477 > > Signed-off-by: Amit Singh Tomar <amittome...@gmail.com> Reviewed-by: Andre Przywara <andre.przyw...@arm.com> Tested-by: Andre Przywara <andre.przyw...@arm.com&

Re: [Xen-devel] [PATCH v3 1/2] xen/arm: Add MVEBU UART driver for Marvell Armada 3700 SoC

ct serial_port *port) > +{ > +struct mvebu3700_uart *uart = port->uart; > +uint32_t reg; > + > +reg = mvebu3700_read(uart, UART_CTRL_REG); > +reg &= ~CTRL_TX_RDY_INT; > +mvebu3700_write(uart, UART_CTRL_REG, reg); > +} > + > +static void mvebu3

Re: [Xen-devel] [PATCH v3 2/2] xen/arm: Add Marvell ARMADA 3700 early printk support

Hi, On 05/04/18 11:16, Amit Singh Tomar wrote: > Signed-off-by: Amit Singh Tomar <amittome...@gmail.com> Reviewed-by: Andre Przywara <andre.przyw...@arm.com> Cheers, Andre. > --- > Changes since v2: > * Addressed Andre's comments. > Changes since v1: > *

Re: [Xen-devel] [PATCH v2 1/2] xen/arm: Add MVEBU UART driver for Marvell Armada 3700 SoC

Hi, On 03/04/18 14:49, Amit Singh Tomar wrote: > This patch adds driver for UART controller found on Armada 3700 SoC. > > There is no reference manuals available for 3700 SoC in public and it > is derived by looking at Linux driver[1]. > >

Re: [Xen-devel] [PATCH v2 2/2] xen/arm: Add Marvell ARMADA 3700 early printk support

Hi, one more thing ... On 04/04/18 16:34, Andre Przywara wrote: > Hi, > > On 03/04/18 14:49, Amit Singh Tomar wrote: >> diff --git a/xen/arch/arm/arm64/debug-mvebu.inc >> b/xen/arch/arm/arm64/debug-mvebu.inc >> new file mode 100644 >> index 000..ac48

Re: [Xen-devel] [PATCH v2 2/2] xen/arm: Add Marvell ARMADA 3700 early printk support

Hi, On 03/04/18 14:49, Amit Singh Tomar wrote: > Signed-off-by: Amit Singh Tomar > --- > Changes since v1: > * Removed header file dependency. > > --- > docs/misc/arm/early-printk.txt | 1 + > xen/arch/arm/Rules.mk | 1 + >

Re: [Xen-devel] [PATCH] ARM: new VGIC: evtchn: fix potential race in vcpu_mark_events_pending()

Hi, On 04/04/18 01:04, Stefano Stabellini wrote: > On Tue, 3 Apr 2018, Julien Grall wrote: >> On 29/03/18 18:35, Stefano Stabellini wrote: >>> On Thu, 29 Mar 2018, Andre Przywara wrote: >>>> Stefano pointed out the following situation: >>>> --

[Xen-devel] [PATCH] ARM: new VGIC: evtchn: fix potential race in vcpu_mark_events_pending()

ect the interrupt. The second call is then a NOP. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> --- Hi, this would ideally have been part of a former patch: "[PATCH v3 06/39] ARM: evtchn: Handle level triggered IRQs correctly", but this has been merged already, so this ha

Re: [Xen-devel] [PATCH v3 32/39] ARM: new VGIC: Implement arch_move_irqs()

Hi, On 28/03/18 19:47, Stefano Stabellini wrote: > On Wed, 21 Mar 2018, Andre Przywara wrote: >> When a VCPU moves to another CPU, we need to adjust the target affinity >> of any hardware mapped vIRQs, to observe our "physical-follows-virtual" >> policy. >>

Re: [Xen-devel] [PATCH v3 06/39] ARM: evtchn: Handle level triggered IRQs correctly

Hi, On 28/03/18 18:46, Stefano Stabellini wrote: > On Wed, 28 Mar 2018, Andre Przywara wrote: >> On 28/03/18 01:01, Stefano Stabellini wrote: >>> On Wed, 21 Mar 2018, Andre Przywara wrote: >>>> The event channel IRQ has level triggered semantics, however the curre

Re: [Xen-devel] [PATCH v3 06/39] ARM: evtchn: Handle level triggered IRQs correctly

Hi, On 28/03/18 01:01, Stefano Stabellini wrote: > On Wed, 21 Mar 2018, Andre Przywara wrote: >> The event channel IRQ has level triggered semantics, however the current >> VGIC treats everything as edge triggered. >> To correctly process those IRQs, we have to lower t

Re: [Xen-devel] [PATCH v3 20/39] ARM: new VGIC: Add PENDING registers handlers

Hi, On 27/03/18 22:14, Stefano Stabellini wrote: > On Wed, 21 Mar 2018, Andre Przywara wrote: >> The pending register handlers are shared between the v2 and v3 >> emulation, so their implementation goes into vgic-mmio.c, to be easily >> referenced from the v3 emulation as wel

Re: [Xen-devel] [PATCH v3 18/39] ARM: new VGIC: Add CTLR, TYPER and IIDR handlers

Hi, On 27/03/18 21:38, Stefano Stabellini wrote: > On Wed, 21 Mar 2018, Andre Przywara wrote: >> Those three registers are v2 emulation specific, so their implementation >> lives entirely in vgic-mmio-v2.c. Also they are handled in one function, >> as their implementation is

Re: [Xen-devel] [PATCH v3 26/39] ARM: new VGIC: Add SGIPENDR register handlers

Hi, On 27/03/18 23:27, Stefano Stabellini wrote: > On Wed, 21 Mar 2018, Andre Przywara wrote: >> As this register is v2 specific, its implementation lives entirely >> in vgic-mmio-v2.c. >> This register allows setting the source mask of an IPI. >> >> This is b

Re: [Xen-devel] [PATCH v3 29/39] ARM: new VGIC: Handle virtual IRQ allocation/reservation

Hi, On 27/03/18 23:38, Stefano Stabellini wrote: > On Wed, 21 Mar 2018, Andre Przywara wrote: >> To find an unused virtual IRQ number Xen uses a scheme to track used >> virtual IRQs. >> Implement this interface in the new VGIC to make the Xen core/arch code >> happy. &

Re: [Xen-devel] [PATCH v3 19/39] ARM: new VGIC: Add ENABLE registers handlers

Hi, On 27/03/18 22:06, Stefano Stabellini wrote: > On Wed, 21 Mar 2018, Andre Przywara wrote: >> As the enable register handlers are shared between the v2 and v3 >> emulation, their implementation goes into vgic-mmio.c, to be easily >> referenced from the v3 em

Re: [Xen-devel] [PATCH v3a 14/39] ARM: new VGIC: Add GICv2 world switch backend

Hi, On 27/03/18 00:22, Stefano Stabellini wrote: > On Thu, 22 Mar 2018, Andre Przywara wrote: >> Processing maintenance interrupts and accessing the list registers >> are dependent on the host's GIC version. >> Introduce vgic-v2.c to contain GICv2 specific functions. &

Re: [Xen-devel] [PATCH v3 13/39] ARM: new VGIC: Add IRQ sync/flush framework

Hi, On 26/03/18 22:30, Stefano Stabellini wrote: > On Wed, 21 Mar 2018, Andre Przywara wrote: >> Implement the framework for syncing IRQs between our emulation and the >> list registers, which represent the guest's view of IRQs. >> This is done in vgic_sync_from_lrs()

Re: [Xen-devel] [PATCH v3 05/39] ARM: timer: Handle level triggered IRQs correctly

Hi, On 26/03/18 21:28, Stefano Stabellini wrote: > On Wed, 21 Mar 2018, Andre Przywara wrote: >> The ARM Generic Timer uses a level-sensitive interrupt semantic. We >> easily catch when the line goes high, as this triggers the hardware IRQ. >> However we also have to keep t

Re: [Xen-devel] [PATCH v3a 14/39] ARM: new VGIC: Add GICv2 world switch backend

Hi, On 22/03/18 14:06, Julien Grall wrote: > Hi Andre, > > On 03/22/2018 11:56 AM, Andre Przywara wrote: >> +    /* The locking order forces us to drop and re-take the locks >> here. */ >> +    if ( irq->hw ) >> +    { >> +    spin_un

Re: [Xen-devel] [PATCH v3a 14/39] ARM: new VGIC: Add GICv2 world switch backend

Hi, On 22/03/18 14:06, Julien Grall wrote: > Hi Andre, > > On 03/22/2018 11:56 AM, Andre Przywara wrote: >> +    /* The locking order forces us to drop and re-take the locks >> here. */ >> +    if ( irq->hw ) >> +    { >> +    spin_un

[Xen-devel] [PATCH v3a 39/39] ARM: VGIC: wire new VGIC(-v2) files into Xen build system

VGIC. In the moment this is restricted to a vGIC-v2. To make the build system happy, we provide a temporary dummy implementation of vgic_v3_setup_hw() to allow building for now. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> --- Changelog v3 ... v3a: - print panic when trying to run on GI

[Xen-devel] [PATCH v3a 03/39] ARM: GIC: Allow tweaking the active and pending state of an IRQ

the state of an associated hardware IRQ. This takes care of properly setting the _IRQ_INPROGRESS bit. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> --- Changelog v3 ... v3a: - always set/clear _IRQ_INPROGRESS bit (not only for guest IRQs) - add comments Changelog v2 ... v3: - extend co

[Xen-devel] [PATCH v3a 14/39] ARM: new VGIC: Add GICv2 world switch backend

the host GIC addresses. This is based on Linux commit 140b086dd197, written by Marc Zyngier. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> --- Changelog v3 ... v3a: - take hardware IRQ lock in vgic_v2_fold_lr_state() - fix last remaining u32 usage - print message when using ne

[Xen-devel] [PATCH v3a 00/39] (0/3) Fixups for the new VGIC(-v2) implementation

Hi, this is just an update of the three patches which didn't get any review tags so far. The fixes for the new versions of 03/39 and 39/39 are pretty straight forward, but 14/39 is more of a beast. I sent a diff to the original patch [1] separately to give an idea of the changes. I added the

Re: [Xen-devel] [PATCH v3 34/39] ARM: new VGIC: vgic-init: register VGIC

Hi, On 22/03/18 08:00, Julien Grall wrote: > Hi Andre, > > On 03/21/2018 04:32 PM, Andre Przywara wrote: >> This patch implements the function which is called by Xen when it wants >> to register the virtual GIC. >> This also implements vgic_max_vcpus() for the new

Re: [Xen-devel] [PATCH v3 15/39] ARM: new VGIC: Implement vgic_vcpu_pending_irq

Hi, On 22/03/18 03:52, Julien Grall wrote: > Hi Andre, > > On 03/21/2018 04:32 PM, Andre Przywara wrote: >> Tell Xen whether a particular VCPU has an IRQ that needs handling >> in the guest. This is used to decide whether a VCPU is runnable or >> if a hypercall

Re: [Xen-devel] [PATCH v3 03/39] ARM: GIC: Allow tweaking the active and pending state of an IRQ

Hi, On 22/03/18 01:51, Julien Grall wrote: > Hi Andre, > > On 03/21/2018 04:31 PM, Andre Przywara wrote: >> When playing around with hardware mapped, level triggered virtual IRQs, >> there is the need to explicitly set the active or pending state of an >> interrupt a

Re: [Xen-devel] [PATCH v3 14/39] ARM: new VGIC: Add GICv2 world switch backend

ease let me know if it's me not being smart enough here instead ;-) Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> --- Hi, will send a proper, merged v3a version of the patch separately. Cheers, Andre xen/arch/arm/vgic/vgic-v2.c | 43 ++

Re: [Xen-devel] [PATCH v3 39/39] ARM: VGIC: wire new VGIC(-v2) files into Xen build system

Hi, On 22/03/18 08:16, Julien Grall wrote: > Hi Andre, > > On 03/21/2018 04:32 PM, Andre Przywara wrote: >> diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c >> index 131358a5a1..22c70ff7cd 100644 >> --- a/xen/arch/arm/vgic/vgic.c >> +++ b/xen/

[Xen-devel] [PATCH v3 29/39] ARM: new VGIC: Handle virtual IRQ allocation/reservation

can't easily reuse the existing implementation. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> Acked-by: Julien Grall <julien.gr...@arm.com> --- xen/arch/arm/vgic/vgic.c | 44 1 file changed, 44 insertions(+) diff --git a/xen/a

[Xen-devel] [PATCH v3 32/39] ARM: new VGIC: Implement arch_move_irqs()

When a VCPU moves to another CPU, we need to adjust the target affinity of any hardware mapped vIRQs, to observe our "physical-follows-virtual" policy. Implement arch_move_irqs() to adjust the physical affinity of all hardware mapped vIRQs targetting this VCPU. Signed-off-by: Andr

[Xen-devel] [PATCH v3 24/39] ARM: new VGIC: Add TARGET registers handlers

of a hardware mapped vIRQ on the way. This is based on Linux commit 2c234d6f1826, written by Andre Przywara. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> Reviewed-by: Julien Grall <julien.gr...@arm.com> --- xen/arch/arm/vgic/vgic-mm

[Xen-devel] [PATCH v3 34/39] ARM: new VGIC: vgic-init: register VGIC

eturn some maximum value if the VGIC has not been initialised yet. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> --- Changelog v2 ... v3: - drop premature #ifdef CONFIG_HAS_GICV3 - use new GIC_INVALID to detect uninitialised VGIC xen/arch/arm/vgic/

[Xen-devel] [PATCH v3 37/39] ARM: new VGIC: vgic-init: implement map_resources

-by: Andre Przywara <andre.przyw...@linaro.org> Acked-by: Julien Grall <julien.gr...@arm.com> --- xen/arch/arm/vgic/vgic-v2.c | 66 + xen/arch/arm/vgic/vgic.h| 1 + 2 files changed, 67 insertions(+) diff --git a/xen/arch/arm/vgic/vgic-v2.

[Xen-devel] [PATCH v3 02/39] ARM: GIC: add GIC_INVALID to enum gic_version

a new first member: GIC_INVALID. Also make it obvious that this has a "0" encoding. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> --- xen/include/asm-arm/gic.h | 1 + 1 file changed, 1 insertion(+) diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h

[Xen-devel] [PATCH v3 12/39] ARM: new VGIC: Add IRQ sorting

Adds the sorting function to cover the case where you have more IRQs to consider than you have LRs. We consider their priorities. This uses the new sort_list() implementation imported from Linux. This is based on Linux commit 8e4447457965, written by Christoffer Dall. Signed-off-by: Andre

[Xen-devel] [PATCH v3 35/39] ARM: new VGIC: Add vgic_v2_enable

Enable the VGIC operation by properly initialising the registers in the hypervisor GIC interface. This is based on Linux commit f7b6985cc3d0, written by Eric Auger. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> Acked-by: Julien Grall <julien.gr...@arm.com> --- Changel

[Xen-devel] [PATCH v3 36/39] ARM: new VGIC: vgic-init: implement vgic_init

to initialize the VGIC. Their prototypes are already in existing header files. This is based on Linux commit ad275b8bb1e6, written by Eric Auger. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> --- Changelog v2 ... v3: - move ROUNDUP(nr_spis) call before boundary check Changelog v1

[Xen-devel] [PATCH v3 39/39] ARM: VGIC: wire new VGIC(-v2) files into Xen build system

VGIC. In the moment this is restricted to a vGIC-v2. To make the build system happy, we provide a temporary dummy implementation of vgic_v3_setup_hw() to allow building for now. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> --- Changelog v2 ... v3: - fix indentation of Kconfig entry - sel

[Xen-devel] [PATCH v3 20/39] ARM: new VGIC: Add PENDING registers handlers

and combine it with the device's level to get the actual pending state. Hardware mapped IRQs need some special handling, as their hardware state has to be coordinated with the virtual pending bit to avoid hanging or masked interrupts. This is based on Linux commit 96b298000db4, written by Andre Przywara

[Xen-devel] [PATCH v3 25/39] ARM: new VGIC: Add SGIR register handler

Triggering an IPI via this register is v2 specific, so the implementation lives entirely in vgic-mmio-v2.c. This is based on Linux commit 55cc01fb9004, written by Andre Przywara. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> --- Changelog v2 ... v3: - fix target mask calcu

[Xen-devel] [PATCH v3 33/39] ARM: new VGIC: Add preliminary stub implementation

The ARM arch code requires an interrupt controller emulation to implement vgic_clear_pending_irqs(), although it is suspected that it is actually not necessary. Go with a stub for now to make the linker happy. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> Reviewed-by: Julien

[Xen-devel] [PATCH v3 30/39] ARM: new VGIC: Dump virtual IRQ info

When we dump guest state on the Xen console, we also print the state of IRQs that are on a VCPU. Add the code to dump the state of an IRQ handled by the new VGIC. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> Acked-by: Julien Grall <julien.gr...@arm.com> --- xen/arch/arm

[Xen-devel] [PATCH v3 04/39] ARM: GIC: Allow reading pending state of a hardware IRQ

the pending state of a particular interrupt. Due to hardware limitations this only works for private interrupts of the current CPU, so there is no CPU field in the prototype. This adds gicv2/3_peek_irq() helper functions, to read a bit in a bitmap spread over several MMIO registers. Signed-off-by: Andre

[Xen-devel] [PATCH v3 06/39] ARM: evtchn: Handle level triggered IRQs correctly

evtchn_upcall_pending variable to make the interrupt line match its status, and call this function upon every hypervisor entry. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> Reviewed-by: Julien Grall <julien.gr...@arm.com> --- xen/arch/arm/domain.c | 7 +++ xen/arch

[Xen-devel] [PATCH v3 14/39] ARM: new VGIC: Add GICv2 world switch backend

the host GIC addresses. This is based on Linux commit 140b086dd197, written by Marc Zyngier. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> --- Changelog v2 ... v3: - remove no longer needed asm/io.h header - replace 0/1 with false/true for bool's - clear _IRQ_INPROGRESS bi

[Xen-devel] [PATCH v3 17/39] ARM: new VGIC: Add GICv2 MMIO handling framework

on Linux commit fb848db39661, written by Andre Przywara. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> Reviewed-by: Julien Grall <julien.gr...@arm.com> --- xen/arch/arm/vgic/vgic-mmio-v2.c | 83 xen/arch/arm/vgic/vgic-mm

[Xen-devel] [PATCH v3 38/39] ARM: new VGIC: Allocate two pages for struct vcpu

, there is no real technical reason this struct has to fit in one page, so lifting the limit to two pages seems like the most pragmatic solution. Restrict this to compiling with the new VGIC and for ARM64 only. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> --- Changelog v2 ... v3: -

[Xen-devel] [PATCH v3 31/39] ARM: new VGIC: Provide system register emulation stub

The Xen arch code traps system registers writes from the guest and will relay anything GIC related to the VGIC. Since this affects only GICv3 (which we don't yet emulate), provide a stub implementation of vgic_emulate() for now. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org>

[Xen-devel] [PATCH v3 26/39] ARM: new VGIC: Add SGIPENDR register handlers

As this register is v2 specific, its implementation lives entirely in vgic-mmio-v2.c. This register allows setting the source mask of an IPI. This is based on Linux commit ed40213ef9b0, written by Andre Przywara. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> Reviewed-by: Julien

[Xen-devel] [PATCH v3 28/39] ARM: new VGIC: Add event channel IRQ handling

The Xen core/arch code relies on two abstracted functions to inject an event channel IRQ and to query its pending state. Implement those to query the state of the new VGIC implementation. Signed-off-by: Andre Przywara <andre.przyw...@linaro.org> Acked-by: Julien Grall <julien.gr..

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