On 13/12/2022 11:50, Jan Beulich wrote:
On 13.12.2022 12:34, David Vrabel wrote:
On 12/12/2022 17:04, Jan Beulich wrote:
On 10.11.2022 17:59, David Vrabel wrote:
--- a/xen/arch/x86/include/asm/msi.h
+++ b/xen/arch/x86/include/asm/msi.h
@@ -237,7 +237,10 @@ struct arch_msix {
int
On 12/12/2022 17:04, Jan Beulich wrote:
On 10.11.2022 17:59, David Vrabel wrote:
--- a/xen/arch/x86/include/asm/msi.h
+++ b/xen/arch/x86/include/asm/msi.h
@@ -237,7 +237,10 @@ struct arch_msix {
int table_refcnt[MAX_MSIX_TABLE_PAGES];
int table_idx[MAX_MSIX_TABLE_PAGES
On 17/11/2022 11:41, Marek Marczykowski-Górecki wrote:
Linux enables MSI-X before disabling INTx, but keeps MSI-X masked until
the table is filled. Then it disables INTx just before clearing MASKALL
bit. Currently this approach is rejected by xen-pciback.
Allow setting PCI_MSIX_FLAGS_ENABLE
?
David
From 837649a70d44455f4fd98e2eaa46dcf35a56d00a Mon Sep 17 00:00:00 2001
From: David Vrabel
Date: Fri, 11 Nov 2022 14:30:16 +
Subject: [PATCH] x86: Always enable memory space decodes when using MSI-X
Instead of the numerous (racy) checks for memory space accesses being
enabled before
) enabled.
Signed-off-by: David Vrabel
SIM: https://t.corp.amazon.com/P63914633
CR: https://code.amazon.com/reviews/CR-79020945
---
xen/arch/x86/include/asm/msi.h | 3 +
xen/arch/x86/msi.c | 215 +
xen/drivers/passthrough/msi.c | 1 +
3 files changed
The main patch in this series is 3/3 with some preparatory patches to
simplify the implementation. To summarize:
Concurrent access the the MSI-X control register are not serialized
with a suitable lock. For example, in msix_capability_init() access
use the pcidevs_lock() but some
r path is not necessary as the
per-vector mask is still still set.
Signed-off-by: David Vrabel
CR: https://code.amazon.com/reviews/CR-79020908
---
xen/arch/x86/msi.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/xen/arch/x86/msi.c b/xen/arch/x86/msi.c
index d0bf
-X table is not accessible) has a
useful warning message.
Signed-off-by: David Vrabel
CR: https://code.amazon.com/reviews/CR-79020927
---
xen/arch/x86/msi.c | 34 +-
1 file changed, 9 insertions(+), 25 deletions(-)
diff --git a/xen/arch/x86/msi.c b/xen/arch/x86
On 27/04/2022 19:03, Andrew Cooper wrote:
On 19/04/2022 16:03, David Vrabel wrote:
From: David Vrabel
If the direct map is incorrectly modified with interrupts disabled,
the required TLB flushes are degraded to flushing the local CPU only.
This could lead to very hard to diagnose problems
On 26/04/2022 15:14, Julien Grall wrote:
Hi,
On 26/04/2022 15:01, Jan Beulich wrote:
On 25.04.2022 15:28, David Vrabel wrote:
--- a/xen/common/page_alloc.c
+++ b/xen/common/page_alloc.c
@@ -162,6 +162,13 @@
static char __initdata opt_badpage[100] = "";
string_para
On 25/04/2022 14:43, Julien Grall wrote:
Hi Jan,
On 25/04/2022 14:37, Jan Beulich wrote:
On 25.04.2022 15:34, Julien Grall wrote:
On 25/04/2022 14:28, David Vrabel wrote:
--- a/xen/common/page_alloc.c
+++ b/xen/common/page_alloc.c
@@ -162,6 +162,13 @@
static char __initdata opt_badpage
From: David Vrabel
Heap pages can only be safely allocated and freed with interuupts
enabled as they may require a TLB flush which will send IPIs (on x86).
Normally spinlock debugging would catch calls from the incorrect
context, but not from stop_machine_run() action functions
From: David Vrabel
Heap pages can only be safely allocated and freed with interuupts
enabled as they may require a TLB flush which will send IPIs.
Normally spinlock debugging would catch calls from the incorrect
context, but not from stop_machine_run() action functions as these are
called
On 21/04/2022 12:38, Jan Beulich wrote:
On 21.04.2022 12:43, David Vrabel wrote:
--- a/xen/arch/arm/setup.c
+++ b/xen/arch/arm/setup.c
@@ -984,6 +984,8 @@ void __init start_xen(unsigned long boot_phys_offset,
console_init_postirq();
+system_state = SYS_STATE_smp_boot
From: David Vrabel
Heap pages can only be safely allocated and freed with interuupts
enabled as they may require a TLB flush which will send IPIs.
Normally spinlock debugging would catch calls from the incorrect
context, but not from stop_machine_run() action functions as these are
called
On 20/04/2022 07:26, Jan Beulich wrote:
On 19.04.2022 17:01, David Vrabel wrote:
From: David Vrabel
Heap pages can only be safely allocated and freed with interuupts
enabled as they may require a TLB flush which will send IPIs.
Enhance the assertions in alloc_xenheap_pages
From: David Vrabel
If the direct map is incorrectly modified with interrupts disabled,
the required TLB flushes are degraded to flushing the local CPU only.
This could lead to very hard to diagnose problems as different CPUs will
end up with different views of memory. Although, no such issues
From: David Vrabel
Heap pages can only be safely allocated and freed with interuupts
enabled as they may require a TLB flush which will send IPIs.
Enhance the assertions in alloc_xenheap_pages() and
alloc_domheap_pages() to check interrupts are enabled. For consistency
the same asserts are used
On 23/03/2022 15:43, Rahul Singh wrote:
in dom0less system. This patch introduce the new feature to support the
signaling between two domUs in dom0less system.
Signed-off-by: Rahul Singh
---
docs/designs/dom0less-evtchn.md | 96 +
1 file changed, 96
of these cases.
Reviewed-by: David Vrabel
David
On 17/03/2022 06:28, Juergen Gross wrote:
On 16.03.22 19:38, Raphael Ning wrote:
From: Raphael Ning
Currently, evtchn_fifo_set_pending() will mark the event as PENDING even
if it fails to lock the FIFO event queue(s), or if the guest has not
initialized the FIFO control block for the
masking/faulting.
Move both pieces of logic from machine_crash_shutdown() to machine_kexec(),
the latter being common for all kexec transitions. Adjust the condition for
CET being considered active to check in CR4, which is simpler and more robust.
Reviewed-by: David Vrabel
Fixes: 311434bfc9d1
kexec_reloc (see xen/arch/x86/x86_64/kexec_reloc.S) has an indirect
branch as part of switching page tables. I understand that if CET-IBT is
enabled this will raise an exception since there's no ENDBR64
instruction and (as far as I could tell) CET-IBT has not been disabled
in machine_kexec()
On 07/03/2022 14:03, Jan Beulich wrote:
On 07.03.2022 12:53, Bjoern Doebel wrote:
@@ -104,18 +122,36 @@ void noinline arch_livepatch_revive(void)
int arch_livepatch_verify_func(const struct livepatch_func *func)
{
+BUILD_BUG_ON(sizeof(struct x86_livepatch_meta) !=
On 14/02/2022 12:50, Andrew Cooper wrote:
Control Flow Integrity schemes use toolchain and optionally hardware support
to help protect against call/jump/return oriented programming attacks.
Use cf_check to annotate function pointer targets for the toolchain.
[...]
-static void
On 18/01/2022 08:50, Jan Beulich wrote:
On 13.01.2022 14:41, Jan Beulich wrote:
Calibration logic assumes that the platform timer (HPET or ACPI PM
timer) and the TSC are read at about the same time. This assumption may
not hold when a long latency event (e.g. SMI or NMI) occurs between the
On 14/01/2022 07:08, Jan Beulich wrote:
On 07.01.2022 13:55, David Vrabel wrote:
Amazon's guest transparent live migration work needs another save
record (for event channel upcall vectors). Reserve another HVM context
save record ID for this.
I have to admit that I have reservations: I
On 10/01/2022 22:55, Stefano Stabellini wrote:
I have a patch for Linux that if XENFEAT_xenstore_late_init is present
makes Linux wait for an event notification before initializing xenstore:
https://marc.info/?l=xen-devel=164160299315589
So with v1 of the Xen and Linux patches series:
- Xen
On 07/01/2022 13:45, Andrew Cooper wrote:
printk("Callback via PCI dev %u INTx %u%s\n",
PCI 00:%02x.0 ?
Is this correct? If I remember right, the INTx lines are associated with
a PCI device, with the function then reporting which line it uses.
So Xen neither knows (nor cares) what
On 06/01/2022 16:48, Jan Beulich wrote:
On 06.01.2022 16:54, David Vrabel wrote:
The Windows XENBUS driver sets the per-VCPU LAPIC vector for event
channel interrupts using the HVMOP_set_evtchn_upcall_vector hypercall
(rather than using a vector-type callback in the CALLBACK_IRQ HVM
parameter
Amazon's guest transparent live migration work needs another save
record (for event channel upcall vectors). Reserve another HVM context
save record ID for this.
Signed-off-by: David Vrabel
---
I've added it to the end, keeping the unused ID at 21.
---
xen/include/public/arch-x86/hvm/save.h | 2
Include the type of the callback via and the per-VCPU upcall vector.
Signed-off-by: David Vrabel
---
v2:
- fix style
- make upcall vector output distinguishable from logs prior to this patch
- use fewer lines for callback via.
---
xen/arch/x86/hvm/irq.c | 49
.
Signed-off-by: David Vrabel
---
xen/arch/x86/hvm/hvm.c | 50 --
xen/include/public/arch-x86/hvm/save.h | 12 ++-
2 files changed, 58 insertions(+), 4 deletions(-)
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 350dc396e3..be2e676c4a
Include the type of the callback via and the per-VCPU upcall vector.
Signed-off-by: David Vrabel
---
xen/arch/x86/hvm/irq.c | 31 +++
1 file changed, 27 insertions(+), 4 deletions(-)
diff --git a/xen/arch/x86/hvm/irq.c b/xen/arch/x86/hvm/irq.c
index 52aae4565f
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