On Thu, 2024-03-14 at 16:33 +0100, Jan Beulich wrote:
> On 14.03.2024 15:45, Andrew Cooper wrote:
> > On 13/03/2024 5:27 pm, Andrew Cooper wrote:
> > > Start cleaning it up with ffs() and friends. Across the board,
> > > this adds:
> > >
> > > * Functioning bitops without arch-specific asm
> >
On 14/03/2024 3:33 pm, Jan Beulich wrote:
> On 14.03.2024 15:45, Andrew Cooper wrote:
>> On 13/03/2024 5:27 pm, Andrew Cooper wrote:
>>> Start cleaning it up with ffs() and friends. Across the board, this adds:
>>>
>>> * Functioning bitops without arch-specific asm
>> It turns out that RISC-V
On 14.03.2024 15:45, Andrew Cooper wrote:
> On 13/03/2024 5:27 pm, Andrew Cooper wrote:
>> Start cleaning it up with ffs() and friends. Across the board, this adds:
>>
>> * Functioning bitops without arch-specific asm
>
> It turns out that RISC-V doesn't have a CLZ instruction in the base
>
On 13/03/2024 5:27 pm, Andrew Cooper wrote:
> Start cleaning it up with ffs() and friends. Across the board, this adds:
>
> * Functioning bitops without arch-specific asm
It turns out that RISC-V doesn't have a CLZ instruction in the base
ISA. As a consequence, __builtin_ffs() emits a library
bitops.h is a mess. It has grown organtically over many years, and forces
unreasonable repsonsibilities out into the per-arch stubs.
Start cleaning it up with ffs() and friends. Across the board, this adds:
* Functioning bitops without arch-specific asm
* An option for arches to provide more
