Re: [Xen-devel] [PATCH] x86/splitlock: CPUID and MSR details

2020-02-21 Thread Jan Beulich
On 20.02.2020 20:58, Andrew Cooper wrote: > A splitlock is an atomic operation which crosses a cache line boundary. It > serialises operations in the cache coherency fabric and comes with a > multi-thousand cycle stall. > > Intel Tremont CPUs introduce MSR_CORE_CAPS to enumerate various

Re: [Xen-devel] [PATCH] x86/splitlock: CPUID and MSR details

2020-02-21 Thread Wei Liu
On Thu, Feb 20, 2020 at 07:58:45PM +, Andrew Cooper wrote: > A splitlock is an atomic operation which crosses a cache line boundary. It > serialises operations in the cache coherency fabric and comes with a > multi-thousand cycle stall. > > Intel Tremont CPUs introduce MSR_CORE_CAPS to

[Xen-devel] [PATCH] x86/splitlock: CPUID and MSR details

2020-02-20 Thread Andrew Cooper
A splitlock is an atomic operation which crosses a cache line boundary. It serialises operations in the cache coherency fabric and comes with a multi-thousand cycle stall. Intel Tremont CPUs introduce MSR_CORE_CAPS to enumerate various core-specific features, and MSR_TEST_CTRL to adjust the