On 29.11.2019 15:36, Roger Pau Monné wrote:
> On Fri, Nov 29, 2019 at 12:12:51PM +, Andrew Cooper wrote:
>> I agree that this wants a command line control, but it wants to be
>> enabled by default any time we find ourselves nested on AMD hardware,
>> not just in shim.
>
> Only on AMD hardware
On Fri, Nov 29, 2019 at 12:12:51PM +, Andrew Cooper wrote:
> On 29/11/2019 12:09, Jan Beulich wrote:
> > On 25.11.2019 18:22, Roger Pau Monne wrote:
> >> When using global pages a full tlb flush can only be performed by
> >> toggling the PGE bit in CR4, which is usually quite expensive in terms
On 29/11/2019 12:09, Jan Beulich wrote:
> On 25.11.2019 18:22, Roger Pau Monne wrote:
>> When using global pages a full tlb flush can only be performed by
>> toggling the PGE bit in CR4, which is usually quite expensive in terms
>> of performance when running virtualized. This is specially relevant
On 25.11.2019 18:22, Roger Pau Monne wrote:
> When using global pages a full tlb flush can only be performed by
> toggling the PGE bit in CR4, which is usually quite expensive in terms
> of performance when running virtualized. This is specially relevant on
> AMD hardware, which doesn't have the ab
When using global pages a full tlb flush can only be performed by
toggling the PGE bit in CR4, which is usually quite expensive in terms
of performance when running virtualized. This is specially relevant on
AMD hardware, which doesn't have the ability to do selective CR4
trapping, but can also be
