On 27/03/18 20:41, Stefano Stabellini wrote:
> On Tue, 27 Mar 2018, Andre Przywara wrote:
>> Hi,
>>
>> On 27/03/18 00:22, Stefano Stabellini wrote:
>>> On Thu, 22 Mar 2018, Andre Przywara wrote:
Processing maintenance interrupts and accessing the list registers
are dependent on the
On Tue, 27 Mar 2018, Andre Przywara wrote:
> Hi,
>
> On 27/03/18 00:22, Stefano Stabellini wrote:
> > On Thu, 22 Mar 2018, Andre Przywara wrote:
> >> Processing maintenance interrupts and accessing the list registers
> >> are dependent on the host's GIC version.
> >> Introduce vgic-v2.c to
Hi,
On 27/03/18 00:22, Stefano Stabellini wrote:
> On Thu, 22 Mar 2018, Andre Przywara wrote:
>> Processing maintenance interrupts and accessing the list registers
>> are dependent on the host's GIC version.
>> Introduce vgic-v2.c to contain GICv2 specific functions.
>> Implement the GICv2
On Tue, 27 Mar 2018, Julien Grall wrote:
> Hi,
> Sorry for the formatting.
>
> On Tue, 27 Mar 2018, 07:25 Stefano Stabellini, wrote:
> On Thu, 22 Mar 2018, Andre Przywara wrote:
> > Processing maintenance interrupts and accessing the list registers
> >
On Mon, 26 Mar 2018, Stefano Stabellini wrote:
> On Thu, 22 Mar 2018, Andre Przywara wrote:
> > Processing maintenance interrupts and accessing the list registers
> > are dependent on the host's GIC version.
> > Introduce vgic-v2.c to contain GICv2 specific functions.
> > Implement the GICv2
Hi,
Sorry for the formatting.
On Tue, 27 Mar 2018, 07:25 Stefano Stabellini,
wrote:
> On Thu, 22 Mar 2018, Andre Przywara wrote:
> > Processing maintenance interrupts and accessing the list registers
> > are dependent on the host's GIC version.
> > Introduce vgic-v2.c
On Thu, 22 Mar 2018, Andre Przywara wrote:
> Processing maintenance interrupts and accessing the list registers
> are dependent on the host's GIC version.
> Introduce vgic-v2.c to contain GICv2 specific functions.
> Implement the GICv2 specific code for syncing the emulation state
> into the VGIC
Hi,
On 03/22/2018 03:12 PM, Andre Przywara wrote:
Hi,
On 22/03/18 14:06, Julien Grall wrote:
Hi Andre,
On 03/22/2018 11:56 AM, Andre Przywara wrote:
+ /* The locking order forces us to drop and re-take the locks
here. */
+ if ( irq->hw )
+ {
+
Hi,
On 22/03/18 14:06, Julien Grall wrote:
> Hi Andre,
>
> On 03/22/2018 11:56 AM, Andre Przywara wrote:
>> + /* The locking order forces us to drop and re-take the locks
>> here. */
>> + if ( irq->hw )
>> + {
>> + spin_unlock(>irq_lock);
>> +
>> + desc
Hi,
On 22/03/18 14:06, Julien Grall wrote:
> Hi Andre,
>
> On 03/22/2018 11:56 AM, Andre Przywara wrote:
>> + /* The locking order forces us to drop and re-take the locks
>> here. */
>> + if ( irq->hw )
>> + {
>> + spin_unlock(>irq_lock);
>> +
>> + desc
Hi Andre,
On 03/22/2018 11:56 AM, Andre Przywara wrote:
+/* The locking order forces us to drop and re-take the locks here. */
+if ( irq->hw )
+{
+spin_unlock(>irq_lock);
+
+desc = irq_to_desc(irq->hwintid);
+spin_lock(>lock);
+
Processing maintenance interrupts and accessing the list registers
are dependent on the host's GIC version.
Introduce vgic-v2.c to contain GICv2 specific functions.
Implement the GICv2 specific code for syncing the emulation state
into the VGIC registers.
This also adds the hook to let Xen setup
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