> From: Jan Beulich
> Sent: Wednesday, April 21, 2021 5:23 PM
>
> On 20.04.2021 18:17, Roger Pau Monné wrote:
> > On Tue, Apr 20, 2021 at 05:38:51PM +0200, Jan Beulich wrote:
> >> On 20.04.2021 17:08, Roger Pau Monné wrote:
> >>> On Thu, Apr 02, 2020 at 04:06:06AM +0800, Chao Gao wrote:
>
On Wed, Apr 21, 2021 at 11:23:13AM +0200, Jan Beulich wrote:
>On 20.04.2021 18:17, Roger Pau Monné wrote:
>> On Tue, Apr 20, 2021 at 05:38:51PM +0200, Jan Beulich wrote:
>>> On 20.04.2021 17:08, Roger Pau Monné wrote:
On Thu, Apr 02, 2020 at 04:06:06AM +0800, Chao Gao wrote:
> ---
On 20.04.2021 18:17, Roger Pau Monné wrote:
> On Tue, Apr 20, 2021 at 05:38:51PM +0200, Jan Beulich wrote:
>> On 20.04.2021 17:08, Roger Pau Monné wrote:
>>> On Thu, Apr 02, 2020 at 04:06:06AM +0800, Chao Gao wrote:
--- a/xen/drivers/passthrough/vtd/qinval.c
+++
On Tue, Apr 20, 2021 at 05:38:51PM +0200, Jan Beulich wrote:
> On 20.04.2021 17:08, Roger Pau Monné wrote:
> > On Thu, Apr 02, 2020 at 04:06:06AM +0800, Chao Gao wrote:
> >> --- a/xen/drivers/passthrough/vtd/qinval.c
> >> +++ b/xen/drivers/passthrough/vtd/qinval.c
> >> @@ -442,6 +442,23 @@ int
On 20.04.2021 17:08, Roger Pau Monné wrote:
> On Thu, Apr 02, 2020 at 04:06:06AM +0800, Chao Gao wrote:
>> --- a/xen/drivers/passthrough/vtd/qinval.c
>> +++ b/xen/drivers/passthrough/vtd/qinval.c
>> @@ -442,6 +442,23 @@ int enable_qinval(struct vtd_iommu *iommu)
>> return 0;
>> }
>>
>>
On Thu, Apr 02, 2020 at 04:06:06AM +0800, Chao Gao wrote:
> --- a/xen/drivers/passthrough/vtd/qinval.c
> +++ b/xen/drivers/passthrough/vtd/qinval.c
> @@ -442,6 +442,23 @@ int enable_qinval(struct vtd_iommu *iommu)
> return 0;
> }
>
> +static int vtd_flush_context_noop(struct vtd_iommu
On 20/04/2021 13:50, Jan Beulich wrote:
Alternatively, you could be a bit more
verbose in your request so the other understand the reasoning behind it.
Well, yes, perhaps. But then there's the desire to not repeat oneself
all the time.
Most likely, the time you try to save not expanding
On 20.04.2021 14:39, Julien Grall wrote:
> On 20/04/2021 13:25, Jan Beulich wrote:
>> On 20.04.2021 14:14, Julien Grall wrote:
>>> It is not really my area of expertise but I wanted to jump on one
>>> comment below...
>>>
>>> On 20/04/2021 12:38, Jan Beulich wrote:
On 01.04.2020 22:06, Chao
Hi,
On 20/04/2021 13:25, Jan Beulich wrote:
On 20.04.2021 14:14, Julien Grall wrote:
Hi,
It is not really my area of expertise but I wanted to jump on one
comment below...
On 20/04/2021 12:38, Jan Beulich wrote:
On 01.04.2020 22:06, Chao Gao wrote:
---
Changes in v2:
- verify system
On Tue, Apr 20, 2021 at 01:38:26PM +0200, Jan Beulich wrote:
>On 01.04.2020 22:06, Chao Gao wrote:
>> According to Intel VT-d SPEC rev3.3 Section 6.5, Register-based Invalidation
>> isn't supported by Intel VT-d version 6 and beyond.
>>
>> This hardware change impacts following two scenarios:
On 20.04.2021 14:14, Julien Grall wrote:
> Hi,
>
> It is not really my area of expertise but I wanted to jump on one
> comment below...
>
> On 20/04/2021 12:38, Jan Beulich wrote:
>> On 01.04.2020 22:06, Chao Gao wrote:
>>> ---
>>> Changes in v2:
>>> - verify system suspension and resumption
Hi,
It is not really my area of expertise but I wanted to jump on one
comment below...
On 20/04/2021 12:38, Jan Beulich wrote:
On 01.04.2020 22:06, Chao Gao wrote:
---
Changes in v2:
- verify system suspension and resumption with this patch applied
- don't fall back to register-based
On 01.04.2020 22:06, Chao Gao wrote:
> According to Intel VT-d SPEC rev3.3 Section 6.5, Register-based Invalidation
> isn't supported by Intel VT-d version 6 and beyond.
>
> This hardware change impacts following two scenarios: admin can disable
> queued invalidation via 'qinval' cmdline and use
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