On 2/10/25 10:41, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (17):
docs/devel/loads-stores: Stop mentioning
cpu_physical_memory_write_rom()
system/memory: Factor address_space_is_io() out
target/i386/arch_memory_mapping: Use address_space_memory_is_io()
hw/s390x/sclp:
On Fri Oct 3, 2025 at 10:06 AM CEST, Roger Pau Monné wrote:
> On Thu, Oct 02, 2025 at 07:48:28PM +0200, Alejandro Vallejo wrote:
>> On Thu Oct 2, 2025 at 5:37 PM CEST, Roger Pau Monné wrote:
>> > On Thu, Oct 02, 2025 at 04:48:38PM +0200, Alejandro Vallejo wrote:
>> >> On Thu Oct 2, 2025 at 4:22 PM
On Fri Oct 3, 2025 at 10:18 AM CEST, Roger Pau Monné wrote:
> On Thu, Oct 02, 2025 at 04:56:48PM +0200, Alejandro Vallejo wrote:
>> On Thu Oct 2, 2025 at 4:17 PM CEST, Roger Pau Monné wrote:
>> > On Thu, Oct 02, 2025 at 04:02:00PM +0200, Alejandro Vallejo wrote:
>> >> On Thu Oct 2, 2025 at 3:38 PM
Hi Julien,
On 10/2/25 14:43, Julien Grall wrote:
Hi,
On 02/10/2025 12:10, Milan Djokic wrote:
Hello Andrew,
On 10/2/25 12:10, Andrew Cooper wrote:
On 01/10/2025 9:01 pm, Milan Djokic wrote:
Signed-off-by: Milan Djokic
---
XEN_DOMCTL_get_address_size hypercall is not implemented for arm
(o
On 10/2/25 3:38 PM, Roger Pau Monné wrote:
On Thu, Oct 02, 2025 at 11:37:36AM +0100, Andrew Cooper wrote:
On 02/10/2025 11:22 am, Roger Pau Monne wrote:
Reading from the E9 port if the emergency console is active should return
0xe9 according to the documentation from Bochs:
https://bochs.sour
On Sun, Sep 28, 2025 at 06:02:23PM +0300, Leon Romanovsky wrote:
> +ccio_map_phys(struct device *dev, phys_addr_t phys, size_t size,
> + enum dma_data_direction direction, unsigned long attrs)
> {
> - return ccio_map_single(dev, page_address(page) + offset, size,
> -
It turns out that using the higher level helpers adjacent like this leads to
terrible code generation. Due to -fno-strict-alising, the store into state->
invalidates the read_cr4() address calculation (which is really cpu_info->cr4
under the hood), meaning that it can't be hoisted.
As a result we
... and rdmsr() while here.
Most of these accesses are in fastpaths and do not need serialising behaviour,
but the write side is serialising on all Intel hardware as well as older AMD
hardware.
No functional change.
Signed-off-by: Andrew Cooper
---
CC: Jan Beulich
CC: Roger Pau Monné
---
xen
FRED and IDT differ by a Supervisor Token on the base of the shstk. This
means that switch_stack_and_jump() needs to discard one extra word when FRED
is active.
Fix a typo in the parameter name, which should be shstk_base.
Signed-off-by: Andrew Cooper
Reviewed-by: Jan Beulich
---
CC: Jan Beuli
Under FRED, the SWAPGS instructions is disallowed. Therefore we must use the
MSR path instead.
read_registers() is in the show_registers() path, so this allows Xen to render
it's current state without suffering #UD (and recursing until the stack guard
page is hit).
All hardware with FRED is expe
Under FRED, there's one entrypoint from Ring 3, and one from Ring 0.
FRED gives us a good stack (even for SYSCALL/SYSENTER), and a unified event
frame on the stack, meaing that all software needs to do is spill the GPRs
with a line of PUSHes. Introduce PUSH_AND_CLEAR_GPRS and POP_GPRS for this
pu
FRED provides PENDING_DBG in the the stack frame, avoiding the need to read
%dr6 manually.
Rename do_debug() to handle_DB(), and update it to take a dbg field using
positive polarity.
Introduce a new handle_DB_IDT() which reads %dr6.
No functional change.
Signed-off-by: Andrew Cooper
Reviewed-
With the shadow stack and exception handling adjustements in place, we can now
activate FRED when appropriate. Note that opt_fred is still disabled by
default.
Introduce init_fred() to set up all the MSRs relevant for FRED. FRED uses
MSR_STAR (entries from Ring3 only), and MSR_FRED_SSP_SL0 alias
This is the combined MSR cleanup and FRED series. Some patches of both v2's
have already been committed.
I have moved the MSR_IMM patch out. It's not strictly needed for FRED, and
really needs to go behind Jan's patch to use mergable sections for
altinstructions which is definitely not making 4.
Mirroring the cleanup to rdmsr(), do the same to wrmsr(). It now has the same
API as wrmsrl(), but we'll want to drop that wrapper in due course.
It's telling that almost all remaining users pass in 0. Most are converted
directly to WRMSRNS, but a few are not.
MSR_VIRT_SPEC_CTRL is unconditiona
Under FRED, SETSSBSY is disallowed, and we want to be setting up FRED prior to
setting up shadow stacks. As we still need Supervisor Tokens in IDT mode, we
need mode-specific logic to establish SSP.
In FRED mode, write a Restore Token, RSTORSSP it, and discard the resulting
Previous-SSP token.
N
It is no longer used.
Signed-off-by: Andrew Cooper
Acked-by: Jan Beulich
---
CC: Jan Beulich
CC: Roger Pau Monné
v2:
* New
---
xen/arch/x86/extable.c | 14 --
xen/arch/x86/include/asm/asm_defns.h | 11 ---
xen/arch/x86/include/asm/uaccess.h | 2 --
xen/a
Right now they're inline in {read,write}_gs_shadow(), but we're going to need
to use these elsewhere to support FRED.
No functional change.
Signed-off-by: Andrew Cooper
---
CC: Jan Beulich
CC: Roger Pau Monné
v3:
* Rename to __{rd,wr}gs_shadow()
---
xen/arch/x86/include/asm/fsgsbase.h | 36
On 10/3/25 18:53, Andrew Cooper wrote:
> It turns out that using the higher level helpers adjacent like this leads to
> terrible code generation. Due to -fno-strict-alising, the store into state->
> invalidates the read_cr4() address calculation (which is really cpu_info->cr4
> under the hood), me
This is really a rearrangement to make adding FRED support easier.
No functional change.
Signed-off-by: Andrew Cooper
Acked-by: Jan Beulich
---
CC: Jan Beulich
CC: Roger Pau Monné
v2:
* New
There is a marginal code size improvement:
add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-46 (-46)
On Thu, Oct 02, 2025 at 07:42:38PM -0400, Jason Andryuk wrote:
> Split out AMD SVM and AMD IOMMU, and add myself as a reviewer. Jan,
> Andrew and Roger are set as maintainers as they were for the X86 entry.
>
> Signed-off-by: Jason Andryuk
Thanks for adding yourself!
I have on question below a
On 10/2/25 11:53 AM, Andrew Cooper wrote:
On 01/10/2025 11:09 pm, Saman Dehghan wrote:
This change enables compatibility for measuring code coverage
with Clang versions 14 through 20 by supporting their
respective raw profile formats.
1- Add support for LLVM raw profile versions 8, 9, and 10
2
On Thu, Oct 02, 2025 at 04:56:48PM +0200, Alejandro Vallejo wrote:
> On Thu Oct 2, 2025 at 4:17 PM CEST, Roger Pau Monné wrote:
> > On Thu, Oct 02, 2025 at 04:02:00PM +0200, Alejandro Vallejo wrote:
> >> On Thu Oct 2, 2025 at 3:38 PM CEST, Roger Pau Monné wrote:
> >> > On Thu, Oct 02, 2025 at 11:37
On 10/2/25 4:10 PM, Marek Marczykowski-Górecki wrote:
On Thu, Oct 02, 2025 at 02:05:56PM +0100, Andrew Cooper wrote:
On 12/06/2025 11:07 am, Frediano Ziglio wrote:
For xen.gz file we strip all symbols and have an additional
xen-syms file version with all symbols.
Make xen.efi more coherent str
On Fri, Oct 03, 2025 at 10:09:31AM +0200, Roger Pau Monné wrote:
> On Thu, Oct 02, 2025 at 07:42:38PM -0400, Jason Andryuk wrote:
> > @@ -601,7 +618,8 @@ M: Roger Pau Monné
> > S: Supported
> > L: xen-devel@lists.xenproject.org
> > F: xen/arch/x86/
> > -F: xen/drivers/passthrough/amd/
> >
On Thu Oct 2, 2025 at 8:27 PM CEST, Demi Marie Obenour wrote:
> On 10/2/25 06:10, Andrew Cooper wrote:
>> On 01/10/2025 9:01 pm, Milan Djokic wrote:
>>> Signed-off-by: Milan Djokic
>>>
>>> ---
>>> XEN_DOMCTL_get_address_size hypercall is not implemented for arm (only for
>>> x86)
>>> It would be
Hi Demi,
On 02/10/2025 19:27, Demi Marie Obenour wrote:
On 10/2/25 06:10, Andrew Cooper wrote:
On 01/10/2025 9:01 pm, Milan Djokic wrote:
Signed-off-by: Milan Djokic
---
XEN_DOMCTL_get_address_size hypercall is not implemented for arm (only for x86)
It would be useful to have this hypercall
On Thu, Sep 18, 2025 at 10:51:58AM +0100, Frediano Ziglio wrote:
> Newer compiler can put some constant strings inside constant
> sections (.rodata.cstXX) instead of string sections (.rodata.str1.XX).
> This causes the produced live patch to not apply when such
> strings are produced.
> So treat th
On Thu, Oct 02, 2025 at 07:48:28PM +0200, Alejandro Vallejo wrote:
> On Thu Oct 2, 2025 at 5:37 PM CEST, Roger Pau Monné wrote:
> > On Thu, Oct 02, 2025 at 04:48:38PM +0200, Alejandro Vallejo wrote:
> >> On Thu Oct 2, 2025 at 4:22 PM CEST, Roger Pau Monné wrote:
> >> > On Thu, Oct 02, 2025 at 03:55
On Wed Oct 1, 2025 at 10:01 PM CEST, Milan Djokic wrote:
> Signed-off-by: Milan Djokic
>
> ---
> XEN_DOMCTL_get_address_size hypercall is not implemented for arm (only for
> x86)
> It would be useful to have this hypercall supported for arm64, in order to get
> current guest addressing mode
Why
On Fri, Oct 03, 2025 at 01:18:32PM -0400, John David Anglin wrote:
> On 2025-10-03 11:01 a.m., Jason Gunthorpe wrote:
> > This doesn't actually use the virt at all:
> >
> > offset = ((unsigned long) addr) & ~IOVP_MASK;
> > if((size % L1_CACHE_BYTES) || ((unsigned long)addr % L1_CACHE_BYTES
On 2025-10-03 1:26 p.m., Jason Gunthorpe wrote:
> On Fri, Oct 03, 2025 at 01:18:32PM -0400, John David Anglin wrote:
>> On 2025-10-03 11:01 a.m., Jason Gunthorpe wrote:
>>> This doesn't actually use the virt at all:
>>>
>>> offset = ((unsigned long) addr) & ~IOVP_MASK;
>>> if((size % L1_CAC
On Sun, Sep 28, 2025 at 06:02:21PM +0300, Leon Romanovsky wrote:
> From: Leon Romanovsky
>
> Alpha doesn't need struct *page and can perform mapping based on
> physical addresses. So convert it to implement new .map_phys callback.
>
> As part of this change, remove useless BUG_ON() as DMA mappin
On 9/29/25 04:41, Roger Pau Monne wrote:
> I've had the luck to come across a PCI card that exposes a MSI-X capability
> where the BIR of the vector and PBA tables points at a BAR that has 0 size.
>
> This doesn't play nice with the code in vpci_make_msix_hole(), as it would
> still use the addres
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