From: FionaLi <fion...@zhaoxin.com>
Signed-off-by: Fiona Li<fion...@zhaoxin.com>
---
xen/arch/x86/cpu/Makefile | 1 +
xen/arch/x86/cpu/common.c | 1 +
xen/arch/x86/cpu/shanghai.c | 61 +++
xen/include/asm-x86/iommu.h
Assigning cpu to cpupool needn't to switch cpu scheduler when
system state is resume, otherwise it will cause ASSERT in
schedule_cpu_switch().
Signed-off-by: FionaLi-oc
---
xen/common/cpupool.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/xen/common/cpupool.c b
When executing SYSEXIT or SYSENTRY in Zhaoxin CPU, CPU needs to
save or restore a set of MSRs.
Signed-off-by: FionaLi-oc
---
xen/arch/x86/acpi/suspend.c | 6 --
xen/arch/x86/x86_64/traps.c | 3 ++-
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/xen/arch/x86/acpi/suspend.c b
Implementation of Zhaoxin CPU frequency is compatible with Intel.
Zhaoxin CPU also supports EST.
Signed-off-by: FionaLi-oc
---
xen/arch/x86/acpi/cpufreq/cpufreq.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/xen/arch/x86/acpi/cpufreq/cpufreq.c
b/xen/arch
The patchset supports some features for Zhaoxin CPU whose vendor
ID is 'Shanghai'. Zhaoxin x86 SOC supports I/O virtualization
which is compatible with Intel I/O virtulizaiton.
Indent with four spaces.
Signed-off-by: FionaLi-oc
---
xen/include/asm-x86/iommu.h | 9 +
1 file changed, 5
When executing SYSEXIT or SYSENTRY in Zhaoxin CPU, CPU needs to
save or restore a set of MSRs.
Signed-off-by: FionaLi-oc
---
xen/arch/x86/acpi/suspend.c | 6 --
xen/arch/x86/x86_64/traps.c | 3 ++-
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/xen/arch/x86/acpi/suspend.c b
Andrew，
Do I need to submit a v3 with cpu_has_sep based solution? Or do you deal with
it?
> -Original Message-
> From: Andrew Cooper
> Sent: Thursday, April 25, 2019 9:42 PM
> To: Jan Beulich ; FionaLi-oc
> Cc: Roger Pau Monne ; Wei Liu ;
> xen-devel ; Cobe Chen(BJ-RD
