On 07/18/2018 03:27 PM, Manish Jaggi wrote:
On 07/02/2018 07:51 PM, Roger Pau Monné wrote:
External Email
On Mon, Jul 02, 2018 at 04:16:05PM +0530, Manish Jaggi wrote:
Hi All,
PCI-PT and PCI config space emulation have been in discussion for
quite a
long time.
We had started some work
On 07/02/2018 07:51 PM, Roger Pau Monné wrote:
External Email
On Mon, Jul 02, 2018 at 04:16:05PM +0530, Manish Jaggi wrote:
Hi All,
PCI-PT and PCI config space emulation have been in discussion for quite a
long time.
We had started some work on this in past and in LEG-XEN but that didnt go
Hi All,
PCI-PT and PCI config space emulation have been in discussion for quite
a long time.
We had started some work on this in past and in LEG-XEN but that didnt
go far and the group is closed.
I believe that PCI-PT is a feature which would be suitable for not only
for servers but for
Hi Sameer,
On 06/08/2018 05:17 AM, Sameer Goel wrote:
Pull common defines for SMMU drives in a local header.
Can add more detail in commit message?
Signed-off-by: Sameer Goel
---
xen/drivers/passthrough/arm/smmu-v3.c | 96 +---
xen/drivers/passthrough/arm/smmu.c|
Hi Stefano,
On 06/04/2018 10:53 PM, Stefano Stabellini wrote:
Hi all,
This patch series is the first step toward building a small certifiable
Xen hypervisor for ARM boards.
How much code size can be reduced ? any ballpark figure
First, the series makes a few changes to allow disabling more
On 06/02/2018 12:28 AM, Sameer Goel wrote:
On 5/31/2018 11:16 PM, Manish Jaggi wrote:
On 05/31/2018 09:27 PM, Sameer Goel wrote:
On 5/30/2018 10:13 PM, Manish Jaggi wrote:
On 05/31/2018 04:31 AM, Sameer Goel wrote:
+
+static int arm_smmu_iommu_domain_init(struct domain *d)
Where
On 05/31/2018 09:27 PM, Sameer Goel wrote:
On 5/30/2018 10:13 PM, Manish Jaggi wrote:
On 05/31/2018 04:31 AM, Sameer Goel wrote:
+
+static int arm_smmu_iommu_domain_init(struct domain *d)
Where is iommu_domain initialized?
The function does not use a iommu_domain * variable
Please check
On 05/31/2018 04:31 AM, Sameer Goel wrote:
+
+static int arm_smmu_iommu_domain_init(struct domain *d)
Where is iommu_domain initialized?
The function does not use a iommu_domain * variable
Please check iommu.c 2 levels up.
In this function do you see iommu_domain getting allocated or
On 05/31/2018 01:16 AM, Sameer Goel wrote:
Manish, I'll take another look at the variable names. I might not have enough
time :).
On 05/23/2018 10:48 PM, Manish Jaggi wrote:
Hi Sameer,
General Comment, please use appropriate variable names for XXX_domain
structures in code which is xen
the
worse and gracefully handle the case.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index ac39eb5e1d..1b36b104bc 100644
--- a/xen/arch/arm/arm64/vgic-v3-sr.c
+++ b/xen/arch/arm/arm64/vgic-v3-sr.c
@@ -792,6 +
From: Manish Jaggi <manish.ja...@cavium.com>
Function vgic_v3_handle_cpuif_access is called from do_trap_guest_sync
if ARM64_WORKAROUND_CAVIUM_30115 capability is found.
A flag skip_hyp_tail is introduced in struct cpu_info. This flag
is used to skip leave_hypervisor_tai
This patch is ported to xen from linux commit:
eab0b2dc4f6f34147e3d10da49ab8032e15dbea0
A number of Group-0 registers can be handled by the same accessors
as that of Group-1, so let's add the required system register encodings
and catch them in the dispatching function.
Signed-off-by: Manish
and gracefully handle the case.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index 27f5139dcb..ac39eb5e1d 100644
--- a/xen/arch/arm/arm64/vgic-v3-sr.c
+++ b/xen/arch/arm/arm64/vgic-v3-sr.c
@@ -782,6 +
Add MIDR values for Cavium ThunderX1 SoC family: ThunderX1, 81XX, 83XX.
This patch copies the below defines as is from linux kernel code.
arch/arm64/include/asm/cputype.h
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git a/xen/include/asm-arm/processor.h b/xen/include/a
will auto enable workaround
Manish Jaggi (17):
arm: Placeholder code to handle guest GICv3 sysreg accesses at EL2
arm64: vgic-v3: Add ICV_BPR1_EL1 handler
arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler
arm64: vgic-v3: Add accessors for the ICH_APxRn_EL2 registers
Expose ich_read/write_lr
This patch is ported to xen from linux commit:
423de85a98c2b50715a0784a74f6124fbc0b1548
Add a handler for reading/writing the guest's view of the ICC_BPR0_EL1
register, which is located in the ICH_VMCR_EL2.BPR0 field.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git a/xe
From: Manish Jaggi <manish.ja...@cavium.com>
gicv3_ich_read/write_lr functions are duplicated in vgic-v3-sr.c
This is done to make the file independent of the xen vgic code for
handling the errata.
Both the functions in the patch are static, so this patch needs
subsequent patches to c
This patch is ported to xen from linux commit:
fbc48a0011deb3d51cb657ca9c0f9083f41c0665
Add a handler for reading/writing the guest's view of the
ICC_IGRPEN0_EL1 register, which is located in the ICH_VMCR_EL2.VENG0
field.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git
This patch is ported to xen from linux commit
b6f49035b4bf6e2709f2a5fed3107f5438c1fd02
Add a handler for writing the guest's view of the ICC_EOIR1_EL1
register. This involves dropping the priority of the interrupt,
and deactivating it if required (EOImode == 0).
Signed-off-by : Manish Jaggi
interrupt.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index 2192547cc4..c067278499 100644
--- a/xen/arch/arm/arm64/vgic-v3-sr.c
+++ b/xen/arch/arm/arm64/vgic-v3-sr.c
@@ -593,6 +593,27 @@ stati
This patch is ported to xen from linux commit:
f8b630bc542e0368886ae193d3519c832b270359
KVM: arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler
Add a handler for reading/writing the guest's view of ICC_IGRPEN1_EL1
register, which is located in the ICH_VMCR_EL2.VENG1 field.
Signed-off-by: Manish Jaggi
:
690a341577f9adf2c275ababe0dcefe91898bbf0
arm64: Add workaround for Cavium Thunder erratum 30115
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git a/docs/misc/arm/silicon-errata.txt b/docs/misc/arm/silicon-errata.txt
index c9854c39f4..a2546d4bb5 100644
--- a/docs/misc/arm/silicon-errata.txt
+++ b/doc
bitfield extraction)
Since the macro is a dependency both are merged in a single patch
Add a handler for reading/writing the guest's view of the ICC_BPR1_EL1
register, which is located in the ICH_VMCR_EL2.BPR1 field.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git a/xen/ar
From: Manish Jaggi <manish.ja...@cavium.com>
The errata will require emulation of GIC virtual CPU interface in Xen.
Because the hypervisor will update its internal state of the vGIC, we
want to avoid messing up with it. So the errata is handled separately
from the rest of the hypervisor
This patch is a xen port of linux commit
f9e7449c780f688bf61a13dfa8c344afeb4ad6e0.
Add a handler for reading/writing the guest's view of the ICV_AP1Rn_EL1
registers. We just map them to the corresponding ICH_AP(1)Rn_EL2
registers.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff
the interrupt and setting the group
priority as active.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index 8e9318d959..1b47351bbb 100644
--- a/xen/arch/arm/arm64/vgic-v3-sr.c
+++ b/xen/arch/arm/arm64/vgic-v
.
This patch only has accessors, it does not modify the vgic code.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index b49c53d1c5..eea087902c 100644
--- a/xen/arch/arm/arm64/vgic-v3-sr.c
+++ b/xen/arch/arm
Hi Sameer,
General Comment, please use appropriate variable names for XXX_domain
structures in code which is xen specific.
On 05/24/2018 06:16 AM, Sameer Goel wrote:
This driver follows an approach similar to smmu driver. The intent here
is to reuse as much Linux code as possible.
- Glue
On 04/19/2018 04:24 PM, Manish Jaggi wrote:
Sorry for top posting,
is someone working on the comments on this patch?
-Manish
If no one is working this code anymore, I would like to pick it up and
continue maintaining it.
Is it fine with all?
-Regards
Manish
On 03/10/2018 11:23 PM
On 04/05/2018 03:10 PM, Julien Grall wrote:
Hi,
On 02/04/18 12:17, Manish Jaggi wrote:
On 04/02/2018 04:33 PM, Manish Jaggi wrote:
On 03/27/2018 03:48 PM, Marc Zyngier wrote:
On 27/03/18 10:07, Manish Jaggi wrote:
This patch is ported to xen from linux commit
On 04/02/2018 04:33 PM, Manish Jaggi wrote:
On 03/27/2018 03:48 PM, Marc Zyngier wrote:
On 27/03/18 10:07, Manish Jaggi wrote:
This patch is ported to xen from linux commit
b6f49035b4bf6e2709f2a5fed3107f5438c1fd02
KVM: arm64: vgic-v3: Add ICV_EOIR1_EL1 handler
Add a handler for writing
On 03/27/2018 03:48 PM, Marc Zyngier wrote:
On 27/03/18 10:07, Manish Jaggi wrote:
This patch is ported to xen from linux commit
b6f49035b4bf6e2709f2a5fed3107f5438c1fd02
KVM: arm64: vgic-v3: Add ICV_EOIR1_EL1 handler
Add a handler for writing the guest's view of the ICC_EOIR1_EL1
register
Hi Julien,
On 03/21/2018 03:42 PM, Julien Grall wrote:
Title: Please drop the full stop.
On 03/13/2018 03:20 PM, mja...@caviumnetworks.com wrote:
...
+ struct rid_devid_map *rmap;
I am sorry but I still don't see any comment about my comment on the
previous version. For reminder:
"A
On 03/27/2018 05:08 PM, Marc Zyngier wrote:
On 27/03/18 12:27, Manish Jaggi wrote:
On 03/27/2018 04:55 PM, Marc Zyngier wrote:
On 27/03/18 12:15, Manish Jaggi wrote:
On 03/27/2018 04:41 PM, Marc Zyngier wrote:
On 27/03/18 12:07, Manish Jaggi wrote:
On 03/27/2018 04:35 PM, Marc Zyngier
On 03/28/2018 06:18 AM, Julien Grall wrote:
Hi,
Sorry for the formatting.
On Wed, 28 Mar 2018, 04:18 Stefano Stabellini, <sstabell...@kernel.org
<mailto:sstabell...@kernel.org>> wrote:
On Tue, 27 Mar 2018, Marc Zyngier wrote:
> On 27/03/18 11:10, Man
On 03/27/2018 04:55 PM, Marc Zyngier wrote:
On 27/03/18 12:15, Manish Jaggi wrote:
On 03/27/2018 04:41 PM, Marc Zyngier wrote:
On 27/03/18 12:07, Manish Jaggi wrote:
On 03/27/2018 04:35 PM, Marc Zyngier wrote:
On 27/03/18 11:56, Manish Jaggi wrote:
On 03/27/2018 04:15 PM, Marc Zyngier
On 03/27/2018 04:41 PM, Marc Zyngier wrote:
On 27/03/18 12:07, Manish Jaggi wrote:
On 03/27/2018 04:35 PM, Marc Zyngier wrote:
On 27/03/18 11:56, Manish Jaggi wrote:
On 03/27/2018 04:15 PM, Marc Zyngier wrote:
On 27/03/18 11:35, Manish Jaggi wrote:
On 03/27/2018 04:00 PM, Marc Zyngier
On 03/27/2018 04:35 PM, Marc Zyngier wrote:
On 27/03/18 11:56, Manish Jaggi wrote:
On 03/27/2018 04:15 PM, Marc Zyngier wrote:
On 27/03/18 11:35, Manish Jaggi wrote:
On 03/27/2018 04:00 PM, Marc Zyngier wrote:
On 27/03/18 10:07, Manish Jaggi wrote:
This patch is ported to xen from linux
On 03/27/2018 04:26 PM, Marc Zyngier wrote:
On 27/03/18 10:07, Manish Jaggi wrote:
This patch is ported from linux to xen
commit: 2724c11a1df4b22ee966c04809ea0e808f66b04e
(KVM: arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler)
Add a handler for reading the guest's view of the ICV_HPPIR1_EL1
On 03/27/2018 04:28 PM, Marc Zyngier wrote:
On 27/03/18 10:07, Manish Jaggi wrote:
This patch is ported to xen from linux commit:
eab0b2dc4f6f34147e3d10da49ab8032e15dbea0
(KVM: arm64: vgic-v3: Add misc Group-0 handlers)
A number of Group-0 registers can be handled by the same accessors
On 03/27/2018 04:15 PM, Marc Zyngier wrote:
On 27/03/18 11:35, Manish Jaggi wrote:
On 03/27/2018 04:00 PM, Marc Zyngier wrote:
On 27/03/18 10:07, Manish Jaggi wrote:
This patch is ported to xen from linux commit
d70c7b31a60f2458f35c226131f2a01a7a98b6cf
KVM: arm64: vgic-v3: Add ICV_BPR1_EL1
On 03/27/2018 04:00 PM, Marc Zyngier wrote:
On 27/03/18 10:07, Manish Jaggi wrote:
This patch is ported to xen from linux commit
d70c7b31a60f2458f35c226131f2a01a7a98b6cf
KVM: arm64: vgic-v3: Add ICV_BPR1_EL1 handler
Add a handler for reading/writing the guest's view of the ICC_BPR1_EL1
On 03/27/2018 03:31 PM, Marc Zyngier wrote:
On 27/03/18 10:07, Manish Jaggi wrote:
The errata will require to emulate the GIC virtual CPU interface in Xen.
Because the hypervisor will update its internal state of the vGIC, we want
to avoid messing up with it. So the errata is handled
the
worse and gracefully handle the case.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
---
xen/arch/arm/arm64/vgic-v3-sr.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index 14276a4c92..d5dc
:
690a341577f9adf2c275ababe0dcefe91898bbf0
arm64: Add workaround for Cavium Thunder erratum 30115
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
---
docs/misc/arm/silicon-errata.txt | 1 +
xen/arch/arm/Kconfig | 11 +++
xen/arch/arm/cpuerrata.c | 21 +
xen/inclu
vreg_emulate_apxrN which has a if (hsr.sysreg.read)
and based on that calls read and write functions. This code placement
is slight different from linux code, which calls read/write functions
from within switch case.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
---
xen/arch/arm/arm64/v
interrupt.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
---
xen/arch/arm/arm64/vgic-v3-sr.c | 31 +++
xen/include/asm-arm/arm64/sysregs.h | 1 +
2 files changed, 32 insertions(+)
diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v
and gracefully handle the case.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
---
xen/arch/arm/arm64/vgic-v3-sr.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index 201194c713..1427
in the dispatching function.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
---
xen/arch/arm/arm64/vgic-v3-sr.c | 7 +++
xen/include/asm-arm/arm64/sysregs.h | 4
2 files changed, 11 insertions(+)
diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
Add MIDR values for Cavium ThunderX1 SoC family: ThunderX1, 81XX, 83XX.
This patch copies the below defines as is from linux kernel code.
arch/arm64/include/asm/cputype.h
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
---
xen/include/asm-arm/processor.h | 9 +
1 file chan
andleave_hypervisor_tail are
invoked in sync, if one is not called other one should be skipped,
otherwise guest vGIC state be out-of-date.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
---
xen/arch/arm/arm64/Makefile | 1 +
xen/arch/arm/traps.c
This patch is ported to xen from linux commit:
423de85a98c2b50715a0784a74f6124fbc0b1548
(KVM: arm64: vgic-v3: Add ICV_BPR0_EL1 handler)
Add a handler for reading/writing the guest's view of the ICC_BPR0_EL1
register, which is located in the ICH_VMCR_EL2.BPR0 field.
Signed-off-by: Manish Jaggi
This patch is ported to xen from linux commit:
fbc48a0011deb3d51cb657ca9c0f9083f41c0665
(KVM: arm64: vgic-v3: Add ICV_IGNREN0_EL1 handler)
Add a handler for reading/writing the guest's view of the
ICC_IGRPEN0_EL1 register, which is located in the ICH_VMCR_EL2.VENG0
field.
Signed-off-by: Manish
This patch is ported to xen from linux commit:
f8b630bc542e0368886ae193d3519c832b270359
KVM: arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler
Add a handler for reading/writing the guest's view of ICC_IGRPEN1_EL1
register, which is located in the ICH_VMCR_EL2.VENG1 field.
Signed-off-by: Manish Jaggi
.
This patch only has accessors, it does not modify the vgic code.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
---
xen/arch/arm/arm64/vgic-v3-sr.c | 93 +
1 file changed, 93 insertions(+)
diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/ar
trap and emulate code
for group0 / group1 registers. Workaround for cavium Errata 30115
needs this emulation code.
vgic_v3_handle_cpuif_access would be called from do_trap_guest_sync
in subsequent patches based on errata macros.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
---
xen/ar
(EOImode == 0).
Signed-off-by : Manish Jaggi <manish.ja...@cavium.com>
---
xen/arch/arm/arm64/vgic-v3-sr.c | 136
xen/include/asm-arm/arm64/sysregs.h | 1 +
xen/include/asm-arm/gic_v3_defs.h | 4 ++
3 files changed, 141 insertions(+)
diff --git
from RFC
- Added commit information on ported patches from linux
- Added skip_hyp_tail to control calling leave_hypervisor_tail
- Added CAVIUM_CONFIG_ERRATUM_30115 which will auto enable workaround
Manish Jaggi (17):
arm: Placeholder for handling Group0/1 traps
arm64: vgic-v3: Add
This patch is ported to xen from linux commit
d70c7b31a60f2458f35c226131f2a01a7a98b6cf
KVM: arm64: vgic-v3: Add ICV_BPR1_EL1 handler
Add a handler for reading/writing the guest's view of the ICC_BPR1_EL1
register, which is located in the ICH_VMCR_EL2.BPR1 field.
Signed-off-by: Manish Jaggi
and the active group
priority, activating the interrupt and setting the group
priority as active.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
---
xen/arch/arm/arm64/vgic-v3-sr.c | 194
xen/include/asm-arm/arm64/sysregs.h | 1 +
xen/include/a
-by: Manish Jaggi <manish.ja...@cavium.com>
---
xen/arch/arm/arm64/vgic-v3-sr.c | 83 +
1 file changed, 83 insertions(+)
diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index 48346ed628..fc5246539e 100644
--- a/xen/arch/arm/arm6
.html
-manish
On 03/16/2018 05:28 PM, Manish Jaggi wrote:
This patch is ported to xen from linux commit
63000dd8006dc987db31ba670edc23142ea91e01
As we're about to access the Active Priority registers a lot more,
let's define accessors that take the register number as a parameter.
This patch only
On 03/21/2018 01:41 PM, Julien Grall wrote:
Hi Manish,
On 03/16/2018 11:58 AM, Manish Jaggi wrote:
This patch is ported to xen from linux commit
d70c7b31a60f2458f35c226131f2a01a7a98b6cf
Add a handler for reading/writing the guest's view of the ICC_BPR1_EL1
register, which is located
Hi Julien,
On 03/21/2018 02:08 PM, Julien Grall wrote:
On 03/16/2018 11:58 AM, Manish Jaggi wrote:
This patch is ported to xen from linux commit:
f8b630bc542e0368886ae193d3519c832b270359
Add a handler for reading/writing the guest's view of the
ICC_IGRPEN1_EL1
The wrapping looks wrong
On 03/23/2018 12:28 PM, Julien Grall wrote:
(Sorry for the formatting)
On 23 Mar 2018 14:46, "Manish Jaggi" <mja...@caviumnetworks.com
<mailto:mja...@caviumnetworks.com>> wrote:
On 03/21/2018 03:26 PM, Julien Grall wrote:
Hi Manish,
On 03/21
On 03/21/2018 03:26 PM, Julien Grall wrote:
Hi Manish,
On 03/21/2018 09:38 AM, Manish Jaggi wrote:
On 03/21/2018 02:15 PM, Julien Grall wrote:
On 03/21/2018 04:58 AM, Manish Jaggi wrote:
Hi Julien,
On 03/20/2018 01:16 PM, Julien Grall wrote:
On 03/16/2018 11:58 AM, Manish Jaggi
On 03/23/2018 06:58 AM, Julien Grall wrote:
Hi Manish,
On 03/13/2018 03:20 PM, mja...@caviumnetworks.com wrote:
From: Manish Jaggi <mja...@caviumnetworks.com>
Structure of Hardware domain's (hwdom) IORT
hwdom's IORT will only have PCIRC nodes and ITS group nodes
in the following
On 03/21/2018 02:15 PM, Julien Grall wrote:
On 03/21/2018 04:58 AM, Manish Jaggi wrote:
Hi Julien,
On 03/20/2018 01:16 PM, Julien Grall wrote:
On 03/16/2018 11:58 AM, Manish Jaggi wrote:
This patchset is a Xen port of Marc's patchset.
arm64: KVM: Mediate access to GICv3 sysregs at EL2
On 03/21/2018 02:59 PM, Julien Grall wrote:
Hi Manish,
Hi Julien,
On 03/13/2018 03:20 PM, mja...@caviumnetworks.com wrote:
From: Manish Jaggi <mja...@caviumnetworks.com>
IORT has a hierarchical structure containing PCIRC nodes, IORT nodes
and SMMU nodes. Each node has with it an
On 03/20/2018 01:13 PM, Julien Grall wrote:
Hi,
On 03/16/2018 11:58 AM, Manish Jaggi wrote:
Some Cavium Thunder CPUs suffer a problem where a Xen guest may
inadvertently cause the host kernel to quit receiving interrupts.
This patch adds CONFIG_CAVIUM_ERRATUM_30115. Subsequent patches
Hi Julien,
On 03/20/2018 01:16 PM, Julien Grall wrote:
On 03/16/2018 11:58 AM, Manish Jaggi wrote:
This patchset is a Xen port of Marc's patchset.
arm64: KVM: Mediate access to GICv3 sysregs at EL2 [1]
The current RFC patchset is a subset of [1], as it handleing only
Group1 traps
as a PoC
Enable trapping for Group0/1 register access when
CONFIG_CAVIUM_ERRATUM_30115 is enabled.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index 473e26111f..6ffed6a634 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gi
This patch is a xen port of linux commit
f9e7449c780f688bf61a13dfa8c344afeb4ad6e0.
Add a handler for reading/writing the guest's view of the ICV_AP1Rn_EL1
registers. We just map them to the corresponding ICH_AP(0/1)Rn_EL2 registers.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
This patch is ported to xen from linux commit:
eab0b2dc4f6f34147e3d10da49ab8032e15dbea0
A number of Group-0 registers can be handled by the same accessors
as that of Group-1, so let's add the required system register encodings
and catch them in the dispatching function.
Signed-off-by: Manish
leave_hypervisor_tail
- Added CAVIUM_CONFIG_ERRATUM_30115 which will auto enable workaround
Manish Jaggi (15):
arm64: cputype: Add MIDR values for Cavium ThunderX1 CPU family
arm64: Add config for Cavium Thunder erratum 30115
arm: Placeholder for handling Group0/1 traps for Cavium Erratum 30115
interrupt.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index 35bad3953f..537e164062 100644
--- a/xen/arch/arm/arm64/vgic-v3-sr.c
+++ b/xen/arch/arm/arm64/vgic-v3-sr.c
@@ -611,6 +611,26 @@ void handle_eoi(
This patch is ported to xen from linux commit
b6f49035b4bf6e2709f2a5fed3107f5438c1fd02
Add a handler for writing the guest's view of the ICC_EOIR1_EL1
register. This involves dropping the priority of the interrupt,
and deactivating it if required (EOImode == 0).
Signed-off-by : Manish Jaggi
This patch is ported to xen from linux commit:
f8b630bc542e0368886ae193d3519c832b270359
Add a handler for reading/writing the guest's view of the
ICC_IGRPEN1_EL1
register, which is located in the ICH_VMCR_EL2.VENG1 field.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git
one should be skipped,
otherwise guest vGIC state be out-of-date.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git a/xen/arch/arm/arm64/Makefile b/xen/arch/arm/arm64/Makefile
index 718fe44455..02cc115239 100644
--- a/xen/arch/arm/arm64/Makefile
+++ b/xen/arch/arm/arm64/Ma
the interrupt and setting the group
priority as active.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index 93ac6f03a9..8af943b37a 100644
--- a/xen/arch/arm/arm64/vgic-v3-sr.c
+++ b/xen/arch/arm/arm64/vgic-v
This patch is ported to xen from linux commit:
423de85a98c2b50715a0784a74f6124fbc0b1548
Add a handler for reading/writing the guest's view of the ICC_BPR0_EL1
register, which is located in the ICH_VMCR_EL2.BPR0 field.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git a/xe
This patch is ported to xen from linux commit:
fbc48a0011deb3d51cb657ca9c0f9083f41c0665
Add a handler for reading/writing the guest's view of the
ICC_IGRPEN0_EL1 register, which is located in the ICH_VMCR_EL2.VENG0
field.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git
This patch is ported to xen from linux commit
d70c7b31a60f2458f35c226131f2a01a7a98b6cf
Add a handler for reading/writing the guest's view of the ICC_BPR1_EL1
register, which is located in the ICH_VMCR_EL2.BPR1 field.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git a/xe
handlers
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index 114d5107a9..1aaade40dc 100644
--- a/xen/arch/arm/arm64/vgic-v3-sr.c
+++ b/xen/arch/arm/arm64/vgic-v3-sr.c
@@ -114,6 +114,98 @@ void handle_igrpen1(
Some Cavium Thunder CPUs suffer a problem where a Xen guest may
inadvertently cause the host kernel to quit receiving interrupts.
This patch adds CONFIG_CAVIUM_ERRATUM_30115. Subsequent patches will
provide workaround.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git a/doc
Add MIDR values for Cavium ThunderX1 SoC family.
ThunderX1, 81XX, 83XX.
Signed-off-by: Manish Jaggi <manish.ja...@cavium.com>
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 65eb1071e1..62ad244785 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/i
Hi Julien,
On 03/13/2018 05:45 PM, Julien Grall wrote:
Hi,
On 12/03/18 12:42, mja...@caviumnetworks.com wrote:
From: Manish Jaggi <manish.ja...@cavium.com>
Rename the menu text to Errata Workarounds. Subsequent patches will
add config options for SoC specific erratas.
Well, yo
correct e-mail address.
sent to Julien Grall <julien.gr...@arm.com> this time.
Cheers,
On 12/03/18 07:49, mja...@caviumnetworks.com wrote:
From: Manish Jaggi <mja...@caviumnetworks.com>
This patch aims to add the support of IORT in Xen. Below is the list
of major components which t
On 10 March 2018 at 23:23, Manish Jaggi <mja...@caviumnetworks.com> wrote:
> Hi Sameer,
>
>
>
> On 02/09/2018 08:40 AM, Sameer Goel wrote:
>>
>> This driver follows an approach similar to smmu driver. The intent here
>> is to reuse as much Linux code as possi
Hi Sameer,
On 02/09/2018 08:40 AM, Sameer Goel wrote:
This driver follows an approach similar to smmu driver. The intent here
is to reuse as much Linux code as possible.
- Glue code has been introduced to bridge the API calls.
- Called Linux functions from the Xen IOMMU function calls.
- Xen
Hi Julien,
On 01/19/2018 12:21 AM, Julien Grall wrote:
diff --git a/xen/include/asm-arm/device.h b/xen/include/asm-arm/device.h
index 6734ae8efd..f78482ca0c 100644
--- a/xen/include/asm-arm/device.h
+++ b/xen/include/asm-arm/device.h
@@ -6,6 +6,8 @@
enum device_type
{
DEV_DT,
+
Hi Julien,
On 01/19/2018 12:21 AM, Julien Grall wrote:
diff --git a/xen/include/asm-arm/device.h b/xen/include/asm-arm/device.h
index 6734ae8efd..f78482ca0c 100644
--- a/xen/include/asm-arm/device.h
+++ b/xen/include/asm-arm/device.h
@@ -6,6 +6,8 @@
enum device_type
{
DEV_DT,
+
On 03/01/2018 08:05 PM, Julien Grall wrote:
Hi,
On 09/02/18 03:10, Sameer Goel wrote:
This patch set adds support for the SMMUv3 driver. This is a
continuation on
a RFCv4.[1]
The IORT support came from [2]. This RFC has some conflicting defines
that
have to be addressed by introducing the
On 02/26/2018 12:12 PM, Manish Jaggi wrote:
On 02/01/2018 04:24 PM, Julien Grall wrote:
Hi Manish,
On 01/02/18 08:51, Manish Jaggi wrote:
On 01/25/2018 11:37 PM, Julien Grall wrote:
Hi,
I forgot to mention one thing about the placement of
do_fixup_vgic_errata.
On 16/01/18 15:42, mja
On 02/01/2018 04:24 PM, Julien Grall wrote:
Hi Manish,
On 01/02/18 08:51, Manish Jaggi wrote:
On 01/25/2018 11:37 PM, Julien Grall wrote:
Hi,
I forgot to mention one thing about the placement of
do_fixup_vgic_errata.
On 16/01/18 15:42, mja...@caviumnetworks.com wrote:
diff --git a/xen
Hi Julien,
On 01/25/2018 07:18 PM, Julien Grall wrote:
Hi Manish,
On 16/01/18 15:42, mja...@caviumnetworks.com wrote:
From: Manish Jaggi <manish.ja...@cavium.com>
Add a config option to enable VGIC Errata Code in Xen. Platforms
which do not
have this errta can compile out this f
Hi Julien,
On 02/05/2018 06:50 PM, Julien Grall wrote:
Hi all,
Arm has recently published a SMC Calling Convention (SMCCC)
specification update [1] that provides an optimised calling convention
and optional, discoverable support for mitigating CVE-2017-5715 (XSA-254
variant 2). ARM Trusted
On 01/25/2018 10:14 PM, Julien Grall wrote:
Hi Manish,
On 16/01/18 15:42, mja...@caviumnetworks.com wrote:
From: Manish Jaggi <manish.ja...@cavium.com>
Add a handler for reading/writing the guest's view of the ICC_BPR1_EL1
register, which is located in the ICH_VMCR_EL2.BPR1
On 01/25/2018 10:22 PM, Julien Grall wrote:
Hi,
On 16/01/18 15:43, mja...@caviumnetworks.com wrote:
From: Manish Jaggi <manish.ja...@cavium.com>
gicv3_ich_read/write_lr functions are static in gic-v3.c
This patch creates wrapper functions which can be used from outside
the file.
On 01/25/2018 10:30 PM, Julien Grall wrote:
Hi Manish,
On 16/01/18 15:43, mja...@caviumnetworks.com wrote:
From: Manish Jaggi <manish.ja...@cavium.com>
In order to be able to trap Group-1 GICv3 system registers, we need to
set ICH_HCR_EL2.TALL1 before entering the guest. This is cont
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