[Xen-devel] [PATCH resend 07/13] arm: Adding ACPI_IORT in arm Kconfig

From: Manish Jaggi Signed-off-by: Manish Jaggi --- xen/arch/arm/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 2782ee6589..d3fbcbcc6f 100644 --- a/xen/arch/arm/Kconfig +++

[Xen-devel] [PATCH resend 12/13] acpi: arm: Provide support for iort iommu configuration hooks

From: Manish Jaggi This patch copies the basic code from linux (iort.c) required to parse IORT and hooks for iommu configuration and initializes smmu device. Provides a top level initcall acpi_iort_init which would call parse_iort (next patch) to parse and prepare the

[Xen-devel] [PATCH resend 08/13] asm: arm: pci: Fix the #include label in asm-arm/pci.h

From: Manish Jaggi asm-arm/pci.h has an incorrect #ifndef label. Fixing it to ARM Signed-off-by: Manish Jaggi --- xen/include/asm-arm/pci.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/include/asm-arm/pci.h

[Xen-devel] [PATCH resend 05/13] acpi: arm: Import acpi_iort.h verbatim from linux 4.14

From: Manish Jaggi Import acpi_iort.h verbatim from linux 4.14 Signed-off-by: Manish Jaggi --- xen/include/asm-arm/acpi/acpi_iort.h | 57 1 file changed, 57 insertions(+) diff --git

[Xen-devel] [PATCH resend 11/13] asm: arm: add pci_domain_nr

From: Manish Jaggi Provide definition for this macro. Signed-off-by: Manish Jaggi --- xen/include/xen/pci.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h index dd5ec43a70..ee1d4dbf93

[Xen-devel] [PATCH resend 06/13] acpi: arm: Update acpi_iort.h with xen specific changes

From: Manish Jaggi Remove the parts of acpi_iort.h which are not required for Xen. Signed-off-by: Manish Jaggi --- xen/include/asm-arm/acpi/acpi_iort.h | 10 ++ 1 file changed, 2 insertions(+), 8 deletions(-) diff --git

[Xen-devel] [PATCH resend 03/13] acpi: arm: Code to generate Hardware Domains IORT

From: Manish Jaggi Structure of Hardware domain's (hwdom) IORT hwdom's IORT will only have PCIRC nodes and ITS group nodes in the following order. SMMU nodes as they are hidden from hardware domain. [IORT Header] [ITS Group 1 ] ... [ITS Group n ] [PCIRC Node 1]

[Xen-devel] [PATCH resend 09/13] asm: arm: to_pci_dev

From: Manish Jaggi to_pci_dev for ARM was todo till now. Provide definition for this macro. Signed-off-by: Manish Jaggi --- xen/drivers/passthrough/arm/smmu.c | 3 ++- xen/include/asm-arm/pci.h | 6 ++ 2 files changed, 8

[Xen-devel] [PATCH resend 00/13] acpi: arm: Add IORT Support

From: Manish Jaggi This patch aims to add the support of IORT in Xen. Below is the list of major components which this patchset provides. a. Add support for parsing the IORT b. Provides API to populate/query requesterid - streamID mappings and reuqesterid -

[Xen-devel] [PATCH resend 02/13] acpi: arm: query estimated size of hardware domain's IORT.

From: Manish Jaggi Code to query estimated IORT size for hardware domain. IORT for hardware domain is generated using the requesterid and deviceid map. Xen code requires the size to be predeterminded. Signed-off-by: Manish Jaggi ---

[Xen-devel] [PATCH resend 01/13] acpi: arm: API: Populate/query rid-devid rid-sid map.

From: Manish Jaggi IORT has a hierarchical structure containing PCIRC nodes, IORT nodes and SMMU nodes. Each node has with it an array of ids and a mapping which maps a range of ids to another node's ids. PCIRC(requesterid)->SMMU(streamid)->ITS(devid) or PCIRC->ITS

[Xen-devel] [PATCH 12/12] arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler

From: Manish Jaggi This patch is ported from linux to xen commit: 2724c11a1df4b22ee966c04809ea0e808f66b04e (KVM: arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler) Add a handler for reading the guest's view of the ICV_HPPIR1_EL1 register. This is a simple parsing of the

[Xen-devel] [PATCH 10/12] arm64: Add ICV_IAR1_EL1 handler

From: Manish Jaggi This patch is ported to xen from linux commit 132a324ab62fe4fb8d6dcc2ab4eddb0e93b69afe. Add a handler for reading the guest's view of the ICC_IAR1_EL1 register. This involves finding the highest priority Group-1 interrupt, checking against both PMR

[Xen-devel] [PATCH 11/12] arm64: vgic-v3: Add ICV_EOIR1_EL1 handler

From: Manish Jaggi This patch is ported to xen from linux commit b6f49035b4bf6e2709f2a5fed3107f5438c1fd02 Add a handler for writing the guest's view of the ICC_EOIR1_EL1 register. This involves dropping the priority of the interrupt, and deactivating it if required

[Xen-devel] [PATCH 08/12] arm64: Add accessors for the ICH_APxRn_EL2 registers

From: Manish Jaggi This patch is ported to xen from linux commit 63000dd8006dc987db31ba670edc23142ea91e01 As we're about to access the Active Priority registers a lot more, let's define accessors that take the register number as a parameter. Signed-off-by: Manish Jaggi

[Xen-devel] [PATCH 07/12] arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler

From: Manish Jaggi This patch is ported to xen from linux commit: f8b630bc542e0368886ae193d3519c832b270359 Add a handler for reading/writing the guest's view of the ICC_IGRPEN1_EL1 register, which is located in the ICH_VMCR_EL2.VENG1 field. Signed-off-by: Manish Jaggi

[Xen-devel] [PATCH 03/12] arm64: Add config for Cavium Thunder erratum 30115

From: Manish Jaggi Some Cavium Thunder CPUs suffer a problem where a KVM guest may inadvertently cause the host kernel to quit receiving interrupts. This patch adds CONFIG_CAVIUM_ERRATUM_30115. Subsequent patches will provide workaround. Signed-off-by: Manish Jaggi

[Xen-devel] [PATCH 00/12] arm64: Mediate access to GICv3 sysregs at EL2

From: Manish Jaggi This patchset is a Xen port of Marc's patchset. arm64: KVM: Mediate access to GICv3 sysregs at EL2 [1] The current RFC patchset is a subset of [1], as it handleing only Group1 traps as a PoC. Most of the trap code is added in vsysreg.c. Trap handler

[Xen-devel] [PATCH 02/12] arm64: cputype: Add MIDR values for Cavium ThunderX1 CPUs

From: Manish Jaggi Add MIDR values for Cavium ThunderX1 SoC's (88xx, 81xx, 83xx). Signed-off-by: Manish Jaggi --- xen/include/asm-arm/processor.h | 9 + 1 file changed, 9 insertions(+) diff --git a/xen/include/asm-arm/processor.h

[Xen-devel] [PATCH 04/12] Enable Group1 Traps by default for Cavium ThunderX1

From: Manish Jaggi Enable trapping for Group1 register access when CONFIG_CAVIUM_ERRATUM_30115 is enabled. Signed-off-by: Manish Jaggi --- xen/arch/arm/gic-v3.c | 16 ++-- xen/include/asm-arm/gic.h | 1 + 2 files changed, 15

[Xen-devel] [PATCH 09/12] Expose ich_read/write_lr in vsysreg_errata.c

From: Manish Jaggi gicv3_ich_read/write_lr functions are duplicated in vsysreg_errata.c Signed-off-by: Manish Jaggi --- xen/arch/arm/arm64/vsysreg_errata.c | 83 + 1 file changed, 83 insertions(+) diff

[Xen-devel] [PATCH 06/12] arm64: vgic-v3: Add ICV_BPR1_EL1 handler

From: Manish Jaggi This patch is ported to xen from linux commit d70c7b31a60f2458f35c226131f2a01a7a98b6cf Add a handler for reading/writing the guest's view of the ICC_BPR1_EL1 register, which is located in the ICH_VMCR_EL2.BPR1 field. Signed-off-by: Manish Jaggi

[Xen-devel] [PATCH 05/12] Placeholder for handling Group1 register traps

From: Manish Jaggi Since this is a SoC errata and trapping of certain group1 registers should not affect the normal flow. A new file vsysreg_errata.c is added. Function vgic_v3_handle_cpuif_access is called from do_trap_guest_sync if ARM64_WORKAROUND_CAVIUM_30115

[Xen-devel] [PATCH 01/12] arm:Kconfig Rename menu text

From: Manish Jaggi Rename the menu text to Errata Workarounds. Subsequent patches will add config options for SoC specific erratas. Signed-off-by: Manish Jaggi --- xen/arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[Xen-devel] [PATCH 12/13] acpi: arm: Provide support for iort iommu configuration hooks

From: Manish Jaggi This patch copies the basic code from linux (iort.c) required to parse IORT and hooks for iommu configuration and initializes smmu device. Provides a top level initcall acpi_iort_init which would call parse_iort (next patch) to parse and prepare the

[Xen-devel] [PATCH 01/13] acpi: arm: API: Populate/query rid-devid rid-sid map.

From: Manish Jaggi IORT has a hierarchical structure containing PCIRC nodes, IORT nodes and SMMU nodes. Each node has with it an array of ids and a mapping which maps a range of ids to another node's ids. PCIRC(requesterid)->SMMU(streamid)->ITS(devid) or PCIRC->ITS

[Xen-devel] [PATCH 09/13] asm: arm: to_pci_dev

From: Manish Jaggi to_pci_dev for ARM was todo till now. Provide definition for this macro. Signed-off-by: Manish Jaggi --- xen/drivers/passthrough/arm/smmu.c | 3 ++- xen/include/asm-arm/pci.h | 6 ++ 2 files changed, 8

[Xen-devel] [PATCH 05/13] acpi: arm: Import acpi_iort.h verbatim from linux 4.14

From: Manish Jaggi Import acpi_iort.h verbatim from linux 4.14 Signed-off-by: Manish Jaggi --- xen/include/asm-arm/acpi/acpi_iort.h | 57 1 file changed, 57 insertions(+) diff --git

[Xen-devel] [PATCH 13/13] Add code to parse IORT and prepare rid maps.

From: Manish Jaggi This patch adds code to parse the pci_rc, idmaps and smmu nodes to - prepare idmaps (rid-sid rid-devid) While resolving the ipmap from pcirc->smmu->its some fixup is required this is done by fixup_rid_devid_map. Signed-off-by: Manish Jaggi

[Xen-devel] [PATCH 04/13] acpi: arm: Copy fwnode / iommu_fwspec code from Linux 4.14

From: Manish Jaggi fwnode is firmware device node object handle type definition. This can be used either for device tree node or ACPI table node. However in the context of this patchset it is used mainly for ACPI nodes. iommu_fwspec defines set of opeations associated

[Xen-devel] [PATCH 07/13] arm: Adding ACPI_IORT in arm Kconfig

From: Manish Jaggi Signed-off-by: Manish Jaggi --- xen/arch/arm/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 2782ee6589..d3fbcbcc6f 100644 --- a/xen/arch/arm/Kconfig +++

[Xen-devel] [PATCH 06/13] acpi: arm: Update acpi_iort.h with xen specific changes

From: Manish Jaggi Remove the parts of acpi_iort.h which are not required for Xen. Signed-off-by: Manish Jaggi --- xen/include/asm-arm/acpi/acpi_iort.h | 10 ++ 1 file changed, 2 insertions(+), 8 deletions(-) diff --git

[Xen-devel] [PATCH 08/13] asm: arm: pci: Fix the #include label in asm-arm/pci.h

From: Manish Jaggi asm-arm/pci.h has an incorrect #ifndef label. Fixing it to ARM Signed-off-by: Manish Jaggi --- xen/include/asm-arm/pci.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/include/asm-arm/pci.h

[Xen-devel] [PATCH 10/13] asm: arm: add dev_is_pci

From: Manish Jaggi dev_is_pci for ARM was todo till now. Provide definition for this macro. Signed-off-by: Manish Jaggi --- xen/include/asm-arm/device.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[Xen-devel] [PATCH 11/13] asm: arm: add pci_domain_nr

From: Manish Jaggi Provide definition for this macro. Signed-off-by: Manish Jaggi --- xen/include/xen/pci.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/include/xen/pci.h b/xen/include/xen/pci.h index dd5ec43a70..ee1d4dbf93

[Xen-devel] [PATCH 02/13] acpi: arm: query estimated size of hardware domain's IORT.

From: Manish Jaggi Code to query estimated IORT size for hardware domain. IORT for hardware domain is generated using the requesterid and deviceid map. Xen code requires the size to be predeterminded. Signed-off-by: Manish Jaggi ---

[Xen-devel] [PATCH 03/13] acpi: arm: Code to generate Hardware Domains IORT

From: Manish Jaggi Structure of Hardware domain's (hwdom) IORT hwdom's IORT will only have PCIRC nodes and ITS group nodes in the following order. SMMU nodes as they are hidden from hardware domain. [IORT Header] [ITS Group 1 ] ... [ITS Group n ] [PCIRC Node 1]

[Xen-devel] [PATCH 00/13] acpi: arm: Add IORT Support

From: Manish Jaggi This patch aims to add the support of IORT in Xen. Below is the list of major components which this patchset provides. a. Add support for parsing the IORT b. Provides API to populate/query requesterid - streamID mappings and reuqesterid -

[Xen-devel] [PATCH 10/10] Enable Trapping of Group1 registers which is controlled by command line

From: Manish Jaggi In order to be able to trap Group-1 GICv3 system registers, we need to set ICH_HCR_EL2.TALL1 before entering the guest. This is controlled by the command line parameter group1_trap. Singed-off-by: Manish Jaggi ---

[Xen-devel] [PATCH 06/10] Expose gicv3_ich_read/write_lr

From: Manish Jaggi gicv3_ich_read/write_lr functions are static in gic-v3.c This patch creates wrapper functions which can be used from outside the file. Signed-off-by: Manish Jaggi --- xen/arch/arm/gic-v3.c| 10 ++

[Xen-devel] [RFC PATCH 02/10] arm64: Add hook to handle guest GICv3 sysreg accesses

From: Manish Jaggi In order to start handling guest access to GICv3 system registers, let's add a hook that will get called when we trap a system register access. This handling code is kept independent of other traps. Set CONFIG_VGIC_ERRATA to enable this code.

[Xen-devel] [PATCH 07/10] arm64: Add ICV_IAR1_EL1 handler

From: Manish Jaggi Add a handler for reading the guest's view of the ICC_IAR1_EL1 register. This involves finding the highest priority Group-1 interrupt, checking against both PMR and the active group priority, activating the interrupt and setting the group priority as

[Xen-devel] [RFC PATCH 00/10] arm64: Mediate access to GICv3 sysregs at EL2

From: Manish Jaggi This patchset is a Xen port of Marc's patchset. arm64: KVM: Mediate access to GICv3 sysregs at EL2 [1] The current RFC patchset is a subset of [1], as it handleing only Group1 traps as a PoC. Most of the trap code is added in vsysreg.c. Trap handler

[Xen-devel] [PATCH 03/10] arm64: Add ICV_BPR1_EL1 handler

From: Manish Jaggi Add a handler for reading/writing the guest's view of the ICC_BPR1_EL1 register, which is located in the ICH_VMCR_EL2.BPR1 field. Signed-off-by: Manish Jaggi --- xen/arch/arm/arm64/vsysreg.c| 71

[Xen-devel] [PATCH 08/10] Add ICV_EOIR1_EL1 handler

From: Manish Jaggi Add a handler for writing the guest's view of the ICC_EOIR1_EL1 register. This involves dropping the priority of the interrupt, and deactivating it if required. Signed-off-by: Manish Jaggi --- xen/arch/arm/arm64/vsysreg.c

[Xen-devel] [PATCH 09/10] arm64: Add a handler for ICV_HPPIR1_EL1

From: Manish Jaggi Add a handler for reading the guest's view of the ICV_HPPIR1_EL1 register. This is a simple parsing of the available LRs, extracting the highest available interrupt. Signed-off-by: Manish Jaggi ---

[Xen-devel] [PATCH 05/10] arm64: Add accessors for the ICH_APxRn_EL2 registers

From: Manish Jaggi define accessors that take the register number as a parameter. Signed-off-by: Manish Jaggi --- xen/arch/arm/arm64/vsysreg.c | 92 1 file changed, 92 insertions(+) diff --git