Hi Stefano,
On 26/06/2019 22:08, Stefano Stabellini wrote:
On Wed, 26 Jun 2019, Julien Grall wrote:
Hi Stefano,
On 6/26/19 8:29 PM, Stefano Stabellini wrote:
On Mon, 10 Jun 2019, Julien Grall wrote:
At the moment BSS is zeroed before the MMU and D-Cache is turned on.
In other words, the
On Wed, 26 Jun 2019, Julien Grall wrote:
> Hi Stefano,
>
> On 6/26/19 8:29 PM, Stefano Stabellini wrote:
> > On Mon, 10 Jun 2019, Julien Grall wrote:
> > > At the moment BSS is zeroed before the MMU and D-Cache is turned on.
> > > In other words, the cache will be bypassed when zeroing the BSS
Hi Stefano,
On 6/26/19 8:29 PM, Stefano Stabellini wrote:
On Mon, 10 Jun 2019, Julien Grall wrote:
At the moment BSS is zeroed before the MMU and D-Cache is turned on.
In other words, the cache will be bypassed when zeroing the BSS section.
Per the Image protocol [1], the state of the cache
On Mon, 10 Jun 2019, Julien Grall wrote:
> At the moment BSS is zeroed before the MMU and D-Cache is turned on.
> In other words, the cache will be bypassed when zeroing the BSS section.
>
> Per the Image protocol [1], the state of the cache for BSS region is not
> known because it is not part of
At the moment BSS is zeroed before the MMU and D-Cache is turned on.
In other words, the cache will be bypassed when zeroing the BSS section.
Per the Image protocol [1], the state of the cache for BSS region is not
known because it is not part of the "loaded kernel image".
This means that the
