On 10/01/18 11:40, Andrew Cooper wrote:
> On 09/01/18 19:39, Juergen Gross wrote:
>> On 09/01/18 20:13, Andrew Cooper wrote:
>>> (sorry for the top-post. I'm on my phone)
>>>
>>> I can see you are using ltr, but I don't see anywhere where where you are
>>> changing the content on the TSS, or the
On 09/01/18 19:39, Juergen Gross wrote:
> On 09/01/18 20:13, Andrew Cooper wrote:
>> (sorry for the top-post. I'm on my phone)
>>
>> I can see you are using ltr, but I don't see anywhere where where you are
>> changing the content on the TSS, or the top-of-stack content.
> The per-vcpu TSS is alr
On 09/01/18 20:13, Andrew Cooper wrote:
> (sorry for the top-post. I'm on my phone)
>
> I can see you are using ltr, but I don't see anywhere where where you are
> changing the content on the TSS, or the top-of-stack content.
The per-vcpu TSS is already initialized with the correct stack
addres
(sorry for the top-post. I'm on my phone)
I can see you are using ltr, but I don't see anywhere where where you are
changing the content on the TSS, or the top-of-stack content.
It is very complicated to safely switch IST stacks when you might be taking
interrupts.
~Andrew
_
On 09/01/18 18:01, Andrew Cooper wrote:
> On 09/01/18 14:27, Juergen Gross wrote:
>> Instead of using the TSS and stacks of the physical processor allocate
>> them per vcpu, map them in the per domain area, and use those.
>>
>> Signed-off-by: Juergen Gross
>
> I don't see anything here which upda
On 09/01/18 14:27, Juergen Gross wrote:
> Instead of using the TSS and stacks of the physical processor allocate
> them per vcpu, map them in the per domain area, and use those.
>
> Signed-off-by: Juergen Gross
I don't see anything here which updates the fields in the TSS across
context switch.
Instead of using the TSS and stacks of the physical processor allocate
them per vcpu, map them in the per domain area, and use those.
Signed-off-by: Juergen Gross
---
xen/arch/x86/domain.c| 45 +++
xen/arch/x86/pv/domain.c | 72
