Re: [Xen-devel] [PATCH v1 01/15] arm64: cputype: Add MIDR values for Cavium ThunderX1 CPU family

2018-03-20 Thread Julien Grall 

Hi Manish,

On 03/16/2018 11:58 AM, Manish Jaggi wrote:

Add MIDR values for Cavium ThunderX1 SoC family.


Did you intend to use a : instead of .?


ThunderX1, 81XX, 83XX.

Signed-off-by: Manish Jaggi 

diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 65eb1071e1..62ad244785 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -43,15 +43,24 @@
  })
  
  #define ARM_CPU_IMP_ARM 0x41

+#define ARM_CPU_IMP_CAVIUM  0x43
  
  #define ARM_CPU_PART_CORTEX_A15 0xC0F

  #define ARM_CPU_PART_CORTEX_A53 0xD03
  #define ARM_CPU_PART_CORTEX_A57 0xD07
  
+#define CAVIUM_CPU_PART_THUNDERX  0x0A1

+#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
+#define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
+
  #define MIDR_CORTEX_A15 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_CORTEX_A15)
  #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_CORTEX_A53)
  #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_CORTEX_A57)
  
+#define MIDR_THUNDERX  MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

+#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, 
CAVIUM_CPU_PART_THUNDERX_81XX)
+#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, 
CAVIUM_CPU_PART_THUNDERX_83XX)
+
  /* MPIDR Multiprocessor Affinity Register */
  #define _MPIDR_UP   (30)
  #define MPIDR_UP(_AC(1,U) << _MPIDR_UP)



--
Julien Grall

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[Xen-devel] [PATCH v1 01/15] arm64: cputype: Add MIDR values for Cavium ThunderX1 CPU family

2018-03-16 Thread Manish Jaggi 
Add MIDR values for Cavium ThunderX1 SoC family.
ThunderX1, 81XX, 83XX.

Signed-off-by: Manish Jaggi 

diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 65eb1071e1..62ad244785 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -43,15 +43,24 @@
 })
 
 #define ARM_CPU_IMP_ARM 0x41
+#define ARM_CPU_IMP_CAVIUM  0x43
 
 #define ARM_CPU_PART_CORTEX_A15 0xC0F
 #define ARM_CPU_PART_CORTEX_A53 0xD03
 #define ARM_CPU_PART_CORTEX_A57 0xD07
 
+#define CAVIUM_CPU_PART_THUNDERX  0x0A1
+#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
+#define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
+
 #define MIDR_CORTEX_A15 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_CORTEX_A15)
 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_CORTEX_A53)
 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, 
ARM_CPU_PART_CORTEX_A57)
 
+#define MIDR_THUNDERX  MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, 
CAVIUM_CPU_PART_THUNDERX)
+#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, 
CAVIUM_CPU_PART_THUNDERX_81XX)
+#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, 
CAVIUM_CPU_PART_THUNDERX_83XX)
+
 /* MPIDR Multiprocessor Affinity Register */
 #define _MPIDR_UP   (30)
 #define MPIDR_UP(_AC(1,U) << _MPIDR_UP)
-- 
2.14.1


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