Re: [Xen-devel] [PATCH v1 06/15] arm64: Add accessors for the ICH_APxRn_EL2 registers

2018-03-26 Thread Marc Zyngier 
On 26/03/18 14:19, Manish Jaggi wrote:
> Hi Marc,
> 
> I have a query on this patch. The original patch was using these 
> functions so it was ok to make them static.
> But this patch is not touching the xen vgic code similar to what your 
> patch did.
> 
> Will it be ok to merge this patch with 
> https://www.spinics.net/lists/arm-kernel/msg587089.html

I can only repeat the argument I try to convey earlier. By changing the
structure of the series, you're making it harder to review it, as it is
not possible to look at two patches side by side and work out what changed.

In the end, that's your call. If you want to change the shape of the
series, go for it. But also appreciate the consequences of doing so.

M.
-- 
Jazz is not dead. It just smells funny...

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Re: [Xen-devel] [PATCH v1 06/15] arm64: Add accessors for the ICH_APxRn_EL2 registers

2018-03-26 Thread Manish Jaggi 

Hi Marc,

I have a query on this patch. The original patch was using these 
functions so it was ok to make them static.
But this patch is not touching the xen vgic code similar to what your 
patch did.


Will it be ok to merge this patch with 
https://www.spinics.net/lists/arm-kernel/msg587089.html


-manish


On 03/16/2018 05:28 PM, Manish Jaggi wrote:

This patch is ported to xen from linux commit
63000dd8006dc987db31ba670edc23142ea91e01

As we're about to access the Active Priority registers a lot more,
let's define accessors that take the register number as a parameter.

This patch only has accessors, another patch will have register trap handlers

Signed-off-by: Manish Jaggi 

diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index 114d5107a9..1aaade40dc 100644
--- a/xen/arch/arm/arm64/vgic-v3-sr.c
+++ b/xen/arch/arm/arm64/vgic-v3-sr.c
@@ -114,6 +114,98 @@ void handle_igrpen1(struct cpu_user_regs *regs, int regidx,
  __vgic_v3_write_igrpen1(regs, regidx);
  }
  
+void  __vgic_v3_write_ap0rn(uint32_t val, int n)

+{
+switch (n)
+{
+case 0:
+WRITE_SYSREG32(val, ICH_AP0R0_EL2);
+break;
+case 1:
+WRITE_SYSREG32(val, ICH_AP0R1_EL2);
+break;
+case 2:
+WRITE_SYSREG32(val, ICH_AP0R2_EL2);
+break;
+case 3:
+WRITE_SYSREG32(val, ICH_AP0R3_EL2);
+break;
+default:
+unreachable();
+}
+}
+
+void __vgic_v3_write_ap1rn(uint32_t val, int n)
+{
+switch (n)
+{
+case 0:
+WRITE_SYSREG32(val, ICH_AP1R0_EL2);
+break;
+case 1:
+WRITE_SYSREG32(val, ICH_AP1R1_EL2);
+break;
+case 2:
+WRITE_SYSREG32(val, ICH_AP1R2_EL2);
+break;
+case 3:
+WRITE_SYSREG32(val, ICH_AP1R3_EL2);
+break;
+default:
+unreachable();
+}
+}
+
+uint32_t  __vgic_v3_read_ap0rn(int n)
+{
+uint32_t val;
+
+switch (n)
+{
+case 0:
+val = READ_SYSREG32(ICH_AP0R0_EL2);
+break;
+case 1:
+val = READ_SYSREG32(ICH_AP0R1_EL2);
+break;
+case 2:
+val = READ_SYSREG32(ICH_AP0R2_EL2);
+break;
+case 3:
+val = READ_SYSREG32(ICH_AP0R3_EL2);
+break;
+default:
+unreachable();
+}
+
+return val;
+}
+
+uint32_t  __vgic_v3_read_ap1rn(int n)
+{
+uint32_t val;
+
+switch (n)
+{
+case 0:
+val = READ_SYSREG32(ICH_AP1R0_EL2);
+break;
+case 1:
+val = READ_SYSREG32(ICH_AP1R1_EL2);
+break;
+case 2:
+val = READ_SYSREG32(ICH_AP1R2_EL2);
+break;
+case 3:
+val = READ_SYSREG32(ICH_AP1R3_EL2);
+break;
+default:
+unreachable();
+}
+
+return val;
+}
+
  bool vgic_v3_handle_cpuif_access(struct cpu_user_regs *regs, const union hsr 
hsr)
  {
  bool ret = true;



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[Xen-devel] [PATCH v1 06/15] arm64: Add accessors for the ICH_APxRn_EL2 registers

2018-03-16 Thread Manish Jaggi 
This patch is ported to xen from linux commit
63000dd8006dc987db31ba670edc23142ea91e01

As we're about to access the Active Priority registers a lot more,
let's define accessors that take the register number as a parameter.

This patch only has accessors, another patch will have register trap handlers

Signed-off-by: Manish Jaggi 

diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index 114d5107a9..1aaade40dc 100644
--- a/xen/arch/arm/arm64/vgic-v3-sr.c
+++ b/xen/arch/arm/arm64/vgic-v3-sr.c
@@ -114,6 +114,98 @@ void handle_igrpen1(struct cpu_user_regs *regs, int regidx,
 __vgic_v3_write_igrpen1(regs, regidx);
 }
 
+void  __vgic_v3_write_ap0rn(uint32_t val, int n)
+{
+switch (n)
+{
+case 0:
+WRITE_SYSREG32(val, ICH_AP0R0_EL2);
+break;
+case 1:
+WRITE_SYSREG32(val, ICH_AP0R1_EL2);
+break;
+case 2:
+WRITE_SYSREG32(val, ICH_AP0R2_EL2);
+break;
+case 3:
+WRITE_SYSREG32(val, ICH_AP0R3_EL2);
+break;
+default:
+unreachable();
+}
+}
+
+void __vgic_v3_write_ap1rn(uint32_t val, int n)
+{
+switch (n)
+{
+case 0:
+WRITE_SYSREG32(val, ICH_AP1R0_EL2);
+break;
+case 1:
+WRITE_SYSREG32(val, ICH_AP1R1_EL2);
+break;
+case 2:
+WRITE_SYSREG32(val, ICH_AP1R2_EL2);
+break;
+case 3:
+WRITE_SYSREG32(val, ICH_AP1R3_EL2);
+break;
+default:
+unreachable();
+}
+}
+
+uint32_t  __vgic_v3_read_ap0rn(int n)
+{
+uint32_t val;
+
+switch (n)
+{
+case 0:
+val = READ_SYSREG32(ICH_AP0R0_EL2);
+break;
+case 1:
+val = READ_SYSREG32(ICH_AP0R1_EL2);
+break;
+case 2:
+val = READ_SYSREG32(ICH_AP0R2_EL2);
+break;
+case 3:
+val = READ_SYSREG32(ICH_AP0R3_EL2);
+break;
+default:
+unreachable();
+}
+
+return val;
+}
+
+uint32_t  __vgic_v3_read_ap1rn(int n)
+{
+uint32_t val;
+
+switch (n)
+{
+case 0:
+val = READ_SYSREG32(ICH_AP1R0_EL2);
+break;
+case 1:
+val = READ_SYSREG32(ICH_AP1R1_EL2);
+break;
+case 2:
+val = READ_SYSREG32(ICH_AP1R2_EL2);
+break;
+case 3:
+val = READ_SYSREG32(ICH_AP1R3_EL2);
+break;
+default:
+unreachable();
+}
+
+return val;
+}
+
 bool vgic_v3_handle_cpuif_access(struct cpu_user_regs *regs, const union hsr 
hsr)
 {
 bool ret = true;
-- 
2.14.1


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