> -Original Message-
> From: Jan Beulich
> Sent: Monday, May 7, 2018 4:24 PM
> To: David Wang
> Cc: xen-devel ; Fiona Li(BJ-RD)
>
> Subject: Re: [PATCH v4] x86/cpu: Add supports for zhaoxin
>>> On 07.05.18 at 12:11, wrote:
>> -Original Message-
>> From: Jan Beulich
>> Sent: Monday, May 7, 2018 4:24 PM
>>
>> >>> On 07.05.18 at 03:37, wrote:
>> > --- a/xen/arch/x86/cpu/intel_cacheinfo.c
>> > +++
>>> On 07.05.18 at 03:37, wrote:
> --- a/xen/arch/x86/cpu/intel_cacheinfo.c
> +++ b/xen/arch/x86/cpu/intel_cacheinfo.c
> @@ -176,7 +176,9 @@ unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c)
>* Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2
From: DavidWang
Zhaoxin is a x86 IC designer. Its SOC products support both CPU
virtualization and I/O virtualization, which are compatible with Intel
VMX and VT-d respectively. Zhaoxin has 'Shanghai' CPU vendor ID.
Signed-off-by: DavidWang
---