On 15/03/2019 10:45, Jan Beulich wrote:
> Judging from insn prefixes, these are scalar insns, but their (memory)
> operands are vector ones (with the exception of 128-bit VMOVDDUP). For
> this some adjustments to disp8scale calculation code are needed.
>
> No explicit test harness additions other
Judging from insn prefixes, these are scalar insns, but their (memory)
operands are vector ones (with the exception of 128-bit VMOVDDUP). For
this some adjustments to disp8scale calculation code are needed.
No explicit test harness additions other than the overrides, as the
compiler already makes
