> From: Roger Pau Monné [mailto:roger@citrix.com]
> Sent: Thursday, December 13, 2018 4:40 PM
>
> On Thu, Dec 13, 2018 at 02:44:00AM +, Tian, Kevin wrote:
> > btw can you also capture ISR/IRR/PPR right before local_irq_enable()?
> > though I didn't see a reason why code in-between may
> From: Jan Beulich [mailto:jbeul...@suse.com]
> Sent: Thursday, December 13, 2018 4:37 PM
>
> >>> On 13.12.18 at 02:28, wrote:
> > btw I checked your original mail:
> >
> > (XEN)[] mwait-idle.c#mwait_idle+0x2a5/0x381
> > xen/arch/x86/cpu/mwait-idle.c:802
> >
> >788 if
On Thu, Dec 13, 2018 at 01:28:23AM +, Tian, Kevin wrote:
> > From: Roger Pau Monné [mailto:roger@citrix.com]
> > Sent: Wednesday, December 12, 2018 8:18 PM
> >
> > On Wed, Dec 12, 2018 at 11:48:52AM +, Tian, Kevin wrote:
> > > > From: Roger Pau Monné [mailto:roger@citrix.com]
> >
On Thu, Dec 13, 2018 at 02:44:00AM +, Tian, Kevin wrote:
> btw can you also capture ISR/IRR/PPR right before local_irq_enable()?
> though I didn't see a reason why code in-between may impact those
> bits, it doesn't hurt to capture the context right before interrupt is
> raised. :-)
I've
>>> On 13.12.18 at 02:28, wrote:
> btw I checked your original mail:
>
> (XEN)[] mwait-idle.c#mwait_idle+0x2a5/0x381
> xen/arch/x86/cpu/mwait-idle.c:802
>
>788if (cpu_is_haltable(cpu))
>789mwait_idle_with_hints(eax,
>
btw can you also capture ISR/IRR/PPR right before local_irq_enable()?
though I didn't see a reason why code in-between may impact those
bits, it doesn't hurt to capture the context right before interrupt is
raised. :-)
> -Original Message-
> From: Tian, Kevin
> Sent: Thursday, December
> From: Roger Pau Monné [mailto:roger@citrix.com]
> Sent: Wednesday, December 12, 2018 8:18 PM
>
> On Wed, Dec 12, 2018 at 11:48:52AM +, Tian, Kevin wrote:
> > > From: Roger Pau Monné [mailto:roger@citrix.com]
> > > Sent: Wednesday, December 12, 2018 7:25 PM
> > >
> > > On Wed, Dec
On Wed, Dec 12, 2018 at 11:48:52AM +, Tian, Kevin wrote:
> > From: Roger Pau Monné [mailto:roger@citrix.com]
> > Sent: Wednesday, December 12, 2018 7:25 PM
> >
> > On Wed, Dec 12, 2018 at 10:36:44AM +, Tian, Kevin wrote:
> > > > From: Roger Pau Monné [mailto:roger@citrix.com]
> >
> From: Roger Pau Monné [mailto:roger@citrix.com]
> Sent: Wednesday, December 12, 2018 7:25 PM
>
> On Wed, Dec 12, 2018 at 10:36:44AM +, Tian, Kevin wrote:
> > > From: Roger Pau Monné [mailto:roger@citrix.com]
> > > Sent: Monday, October 15, 2018 6:30 PM
> > > (XEN) [22642] POWER
On Wed, Dec 12, 2018 at 10:36:44AM +, Tian, Kevin wrote:
> > From: Roger Pau Monné [mailto:roger@citrix.com]
> > Sent: Monday, October 15, 2018 6:30 PM
> > (XEN) [22642] POWERTYPE 4
> > (XEN) [22643] IDLE PPR 0x0020
> > (XEN)IRR
> >
> From: Roger Pau Monné [mailto:roger@citrix.com]
> Sent: Monday, October 15, 2018 6:30 PM
> (XEN) [22642] POWERTYPE 4
> (XEN) [22643] IDLE PPR 0x0020
> (XEN)IRR
> 00
> 00
> (XEN)
> From: Roger Pau Monné [mailto:roger@citrix.com]
> Sent: Wednesday, November 28, 2018 5:20 PM
>
> On Thu, Nov 01, 2018 at 09:18:14AM +, Andrew Cooper wrote:
> > On 01/11/2018 00:40, Tian, Kevin wrote:
> > >> From: Tian, Kevin
> > >> Sent: Tuesday, October 30, 2018 3:00 PM
> > >>
> > >>>
On Thu, Nov 01, 2018 at 09:18:14AM +, Andrew Cooper wrote:
> On 01/11/2018 00:40, Tian, Kevin wrote:
> >> From: Tian, Kevin
> >> Sent: Tuesday, October 30, 2018 3:00 PM
> >>
> >>> From: Jan Beulich [mailto:jbeul...@suse.com]
> >>> Sent: Thursday, October 25, 2018 9:58 PM
> >>>
> >> On
On 01/11/2018 00:40, Tian, Kevin wrote:
>> From: Tian, Kevin
>> Sent: Tuesday, October 30, 2018 3:00 PM
>>
>>> From: Jan Beulich [mailto:jbeul...@suse.com]
>>> Sent: Thursday, October 25, 2018 9:58 PM
>>>
>> On 25.10.18 at 15:02, wrote:
On 25/10/18 13:51, Jan Beulich wrote:
On
> From: Tian, Kevin
> Sent: Tuesday, October 30, 2018 3:00 PM
>
> > From: Jan Beulich [mailto:jbeul...@suse.com]
> > Sent: Thursday, October 25, 2018 9:58 PM
> >
> > >>> On 25.10.18 at 15:02, wrote:
> > > On 25/10/18 13:51, Jan Beulich wrote:
> > > On 15.10.18 at 14:06, wrote:
> > >>> From
>>> On 29.10.18 at 18:06, wrote:
> On 29/10/18 16:58, Jan Beulich wrote:
> On 29.10.18 at 17:44, wrote:
>>> On 29/10/18 16:33, Jan Beulich wrote:
>>> On 15.10.18 at 12:30, wrote:
> (XEN) [22641] PUSH {sp 0, irq 30, vec 0x21}
This is the last push or pop.
>
> From: Jan Beulich [mailto:jbeul...@suse.com]
> Sent: Thursday, October 25, 2018 9:58 PM
>
> >>> On 25.10.18 at 15:02, wrote:
> > On 25/10/18 13:51, Jan Beulich wrote:
> > On 15.10.18 at 14:06, wrote:
> >>> From the debugging, we see that PPR/IRR/ISR appear to retain their
> state
> >>>
On 29/10/18 16:58, Jan Beulich wrote:
On 29.10.18 at 17:44, wrote:
>> On 29/10/18 16:33, Jan Beulich wrote:
>> On 15.10.18 at 12:30, wrote:
(XEN) [22641] PUSH {sp 0, irq 30, vec 0x21}
>>> This is the last push or pop.
>>>
(XEN) [22650] WAKE PPR 0x0020
>>> On 29.10.18 at 17:44, wrote:
> On 29/10/18 16:33, Jan Beulich wrote:
> On 15.10.18 at 12:30, wrote:
>>> (XEN) [22641] PUSH {sp 0, irq 30, vec 0x21}
>> This is the last push or pop.
>>
>>> (XEN) [22650] WAKE PPR 0x0020
>>> (XEN)IRR
>
On 29/10/18 16:33, Jan Beulich wrote:
On 15.10.18 at 12:30, wrote:
>> (XEN) [22641] PUSH {sp 0, irq 30, vec 0x21}
> This is the last push or pop.
>
>> (XEN) [22650] WAKE PPR 0x0020
>> (XEN)IRR
>>
>>> On 15.10.18 at 12:30, wrote:
> (XEN) [22641] PUSH {sp 0, irq 30, vec 0x21}
This is the last push or pop.
> (XEN) [22650] WAKE PPR 0x0020
> (XEN)IRR
> 0200
> (XEN)ISR
>
On Mon, Oct 22, 2018 at 03:33:07PM +0800, Chao Gao wrote:
> Hi, Roger, Andrew and Wei,
>
> Jan's patch
> (https://lists.xen.org/archives/html/xen-devel/2018-10/msg01031.html)
> fixs an issue in handling SVI. Currently, when dealing with EOI from guest,
> the
> SVI was cleared. But the correct
>>> On 25.10.18 at 15:02, wrote:
> On 25/10/18 13:51, Jan Beulich wrote:
> On 15.10.18 at 14:06, wrote:
>>> From the debugging, we see that PPR/IRR/ISR appear to retain their state
>>> across the mwait, and there is nothing in the manual which I can see
>>> discussing the interaction of
On 25/10/18 13:51, Jan Beulich wrote:
On 15.10.18 at 14:06, wrote:
>> From the debugging, we see that PPR/IRR/ISR appear to retain their state
>> across the mwait, and there is nothing in the manual which I can see
>> discussing the interaction of LAPIC state and C states.
> Is it perhaps a
>>> On 15.10.18 at 14:06, wrote:
> From the debugging, we see that PPR/IRR/ISR appear to retain their state
> across the mwait, and there is nothing in the manual which I can see
> discussing the interaction of LAPIC state and C states.
Is it perhaps a bad idea to go idle with an un-acked
On 22/10/2018 08:33, Chao Gao wrote:
> On Mon, Oct 15, 2018 at 01:06:12PM +0100, Andrew Cooper wrote:
>> On 15/10/18 11:30, Roger Pau Monné wrote:
>>> Hello,
>>>
>>> Wei recently discovered an issue when running a Linux PVH Dom0 on a
>>> box with a Intel Family 6 (0x6), Model 158 (0x9e), Stepping
On Mon, Oct 15, 2018 at 01:06:12PM +0100, Andrew Cooper wrote:
>On 15/10/18 11:30, Roger Pau Monné wrote:
>> Hello,
>>
>> Wei recently discovered an issue when running a Linux PVH Dom0 on a
>> box with a Intel Family 6 (0x6), Model 158 (0x9e), Stepping 9 (raw
>> 000906e9) CPU, we are not sure
On 15/10/18 11:30, Roger Pau Monné wrote:
> Hello,
>
> Wei recently discovered an issue when running a Linux PVH Dom0 on a
> box with a Intel Family 6 (0x6), Model 158 (0x9e), Stepping 9 (raw
> 000906e9) CPU, we are not sure whether the issue is limited to a PVH
> Dom0, or it just happens to be
Hello,
Wei recently discovered an issue when running a Linux PVH Dom0 on a
box with a Intel Family 6 (0x6), Model 158 (0x9e), Stepping 9 (raw
000906e9) CPU, we are not sure whether the issue is limited to a PVH
Dom0, or it just happens to be easier to trigger in this scenario.
The issue is
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