On 09/21/2017 12:16 PM, Andrew Cooper wrote:
On 21/09/17 17:00, Boris Ostrovsky wrote:
Signed-off-by: Juergen Gross
---
arch/x86/include/asm/xen/page.h | 11 ++-
arch/x86/xen/mmu_pv.c | 4 ++--
2 files changed, 12 insertions(+), 3
On 21/09/17 17:00, Boris Ostrovsky wrote:
Signed-off-by: Juergen Gross
---
arch/x86/include/asm/xen/page.h | 11 ++-
arch/x86/xen/mmu_pv.c | 4 ++--
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/xen/page.h
On 09/21/2017 10:41 AM, Juergen Gross wrote:
On 21/09/17 16:14, Boris Ostrovsky wrote:
On 09/21/2017 04:01 AM, Juergen Gross wrote:
Physical addresses on processors supporting 5 level paging can be up to
52 bits wide. For a Xen pv guest running on such a machine those
physical addresses
On 21/09/17 16:14, Boris Ostrovsky wrote:
>
>
> On 09/21/2017 04:01 AM, Juergen Gross wrote:
>> Physical addresses on processors supporting 5 level paging can be up to
>> 52 bits wide. For a Xen pv guest running on such a machine those
>> physical addresses have to be supported in order to be
On 09/21/2017 04:01 AM, Juergen Gross wrote:
Physical addresses on processors supporting 5 level paging can be up to
52 bits wide. For a Xen pv guest running on such a machine those
physical addresses have to be supported in order to be able to use any
memory on the machine even if the guest
Physical addresses on processors supporting 5 level paging can be up to
52 bits wide. For a Xen pv guest running on such a machine those
physical addresses have to be supported in order to be able to use any
memory on the machine even if the guest itself does not support 5 level
paging.
So when