Re: [Xen-devel] [PATCH] x86emul: honor MXCSR.MM

2016-10-14 Thread Andrew Cooper
On 14/10/16 07:20, Jan Beulich wrote: On 13.10.16 at 15:26, wrote: >> On 13/10/16 13:57, Jan Beulich wrote: >>> Commit 6dc9ac9f52 ("x86emul: check alignment of SSE and AVX memory >>> operands") didn't consider a specific AMD mode: Mis-alignment #GP >>> faults can

Re: [Xen-devel] [PATCH] x86emul: honor MXCSR.MM

2016-10-14 Thread Jan Beulich
>>> On 13.10.16 at 15:26, wrote: > On 13/10/16 13:57, Jan Beulich wrote: >> Commit 6dc9ac9f52 ("x86emul: check alignment of SSE and AVX memory >> operands") didn't consider a specific AMD mode: Mis-alignment #GP >> faults can be masked on some of their hardware. >> >>

Re: [Xen-devel] [PATCH] x86emul: honor MXCSR.MM

2016-10-13 Thread Andrew Cooper
On 13/10/16 13:57, Jan Beulich wrote: > Commit 6dc9ac9f52 ("x86emul: check alignment of SSE and AVX memory > operands") didn't consider a specific AMD mode: Mis-alignment #GP > faults can be masked on some of their hardware. > > Signed-off-by: Jan Beulich This highlights that