flight 118934 seabios real [real]
http://logs.test-lab.xenproject.org/osstest/logs/118934/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-amd64-xl-qemuu-ws16-amd64 17 guest-stop fail REGR. vs. 115539
Tests which did not suc
Hello,
Thank you for your quick response.
Any hints how can I "fix" this "issue"? *Any workaround?
ᐧ
2018-02-08 18:32 GMT+01:00 Wei Liu :
> On Thu, Feb 08, 2018 at 04:56:00PM +, Anthony PERARD wrote:
> > On Thu, Feb 08, 2018 at 04:48:10PM +, Wei Liu wrote:
> > > On Thu, Feb 08, 2018 at
On 07/02/18 23:22, Simon Gaiser wrote:
> Commit fd8aa9095a95 ("xen: optimize xenbus driver for multiple
> concurrent xenstore accesses") made a subtle change to the semantic of
> xenbus_dev_request_and_reply() and xenbus_transaction_end().
>
> Before on an error response to XS_TRANSACTION_END
> xe
On 12/02/18 09:49, Juergen Gross wrote:
> On 07/02/18 23:22, Simon Gaiser wrote:
>> Commit fd8aa9095a95 ("xen: optimize xenbus driver for multiple
>> concurrent xenstore accesses") made a subtle change to the semantic of
>> xenbus_dev_request_and_reply() and xenbus_transaction_end().
>>
>> Before o
On Mon, Feb 12, 2018 at 09:25:42AM +0800, Haozhong Zhang wrote:
> On 02/09/18 12:33 +, Roger Pau Monné wrote:
> > Thanks for the series, I'm however wondering whether it's appropriate
> > to post a v4 as RFC. Ie: at v4 the reviewer expects the submitter to
> > have a clear picture of what needs
On Fri, 2018-02-09 at 23:53 -0500, Meng Xu wrote:
> >
> > Perhaps Meng has some more ideas on this as well. :-)
>
> If the RT VCPU has only one RT task on it, we can synchronize the
> release time of the VCPU and that of the RT task. In other words, the
> release offset of both the VCPU and the R
Hello Dario,
On 09.02.18 17:18, Dario Faggioli wrote:
So, I'm a little bit in a hurry now, and I'll reply better later (or on
Monday). But for now, just to understand things better, can you enable
extratime for DomR as well, and report what you see in xentop, and
whether or not you still see de
On Sat, Feb 10, 2018 at 12:47:07AM +0800, Chao Gao wrote:
> On Fri, Feb 09, 2018 at 03:11:25PM +, Roger Pau Monné wrote:
> >On Fri, Nov 17, 2017 at 02:22:12PM +0800, Chao Gao wrote:
> >> From: Lan Tianyu
> >>
> >> This patch is to add callback for vIOAPIC and vMSI to check whether
> >> inter
flight 118942 qemu-mainline real [real]
http://logs.test-lab.xenproject.org/osstest/logs/118942/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-armhf-armhf-libvirt-xsm 14 saverestore-support-checkfail like 118670
test-armhf-armhf-libvirt 14 sav
On 12/02/18 01:44, Haozhong Zhang wrote:
> ... and fix the coding style on fly.
>
> valid_numa_range(..., epfn << PAGE_SHIFT, ...) and its only caller
> memory_add(..., epfn, pxm) interpret epfn inconsistently. The former
> interprets epfn as the last pfn, while the latter interprets it as the
> la
On Sat, Feb 10, 2018 at 01:12:28AM +0800, Chao Gao wrote:
> On Fri, Feb 09, 2018 at 04:27:54PM +, Roger Pau Monné wrote:
> >On Fri, Nov 17, 2017 at 02:22:14PM +0800, Chao Gao wrote:
> >> +if ( !vvtd )
> >> +return ENOMEM;
> >> +
> >> +vvtd_reset(vvtd);
> >> +vvtd->base_addr
Hello Meng,
On 10.02.18 06:53, Meng Xu wrote:
If the RT VCPU has only one RT task on it, we can synchronize the
release time of the VCPU and that of the RT task. In other words, the
release offset of both the VCPU and the RT task are the same in terms
of the wall clock. Then we can assign the t
On 08/02/18 12:25, Roger Pau Monne wrote:
> Hello,
>
> The following small series contain one cleanup, one bugfix and finally
> switches PVH Dom0 from whitelisting ACPI tables instead of blacklisting
> them.
>
> The number of allowed tables ATM is fairly limited, many more could be
> added if the r
The idea of a paravirtual IOMMU interface was last discussed on xen-devel
more than two years ago and narrowed down on a draft specification [1].
There was also an RFC patch series posted with an implementation, however
this was never followed through.
In this patch series I have tried to simplify
This patch adds a new method to the VT-d IOMMU implementation to find the
MFN currently mapped by the specified BFN. This functionality will be used
by a subsequent patch.
Signed-off-by: Paul Durrant
---
Cc: Kevin Tian
Cc: Jan Beulich
---
xen/drivers/passthrough/vtd/iommu.c | 39 ++
This patch modifies the methods in struct iommu_ops to use type-safe BFN
and MFN. This follows on from the prior patch that modified the functions
exported in xen/iommu.h.
Signed-off-by: Paul Durrant
---
Cc: Suravee Suthikulpanit
Cc: Jan Beulich
Cc: Kevin Tian
Cc: Andrew Cooper
---
xen/drive
This patch modifies the declaration of the entry points to the IOMMU
sub-system to use bfn_t and mfn_t in place of unsigned long. A subsequent
patch will similarly modify the methods in the iommu_ops structure.
NOTE: Since (with this patch applied) bfn_t is now in use, the patch also
introdu
This patch adds iommu_ops to allow a domain with control_iommu privilege
to map and unmap pages from any guest over which it has mapping privilege
in the IOMMU.
These operations implicitly disable IOTLB flushing so that the caller can
batch operations and then explicitly flush the IOTLB using the i
...meaning 'bus frame number' i.e. a frame number mapped in the IOMMU
rather than the MMU.
This patch is a largely cosmetic change that substitutes the terms 'gfn'
and 'gaddr' for 'bfn' and 'baddr' in all the places where the frame number
or address relate to the IOMMU rather than the MMU.
The on
This patch introduces the boilerplate for a new hypercall to allow a
domain to control IOMMU mappings for its own pages.
Whilst there is duplication of code between the native and compat entry
points which appears ripe for some form of combination, I think it is
better to maintain the separation as
Certain areas of memory, such as RMRRs, must be mapped 1:1
(i.e. BFN == MFN) through the IOMMU.
This patch adds an iommu_op to allow these ranges to be queried.
Signed-off-by: Paul Durrant
---
Cc: Jan Beulich
Cc: Andrew Cooper
Cc: George Dunlap
Cc: Ian Jackson
Cc: Konrad Rzeszutek Wilk
Cc:
On 22/11/17 08:59, Juergen Gross wrote:
> Today Mini-OS will print all console output via the hypervisor, too.
>
> Make this behavior configurable instead and default it to "off".
>
> Signed-off-by: Juergen Gross
> Acked-by: Samuel Thibault
Still pending...
Juergen
_
On 09/11/17 13:45, Wei Liu wrote:
> On Thu, Nov 09, 2017 at 01:35:49PM +0100, Juergen Gross wrote:
>> On 09/11/17 13:31, Wei Liu wrote:
>>> On Thu, Nov 09, 2017 at 01:10:12PM +0100, Juergen Gross wrote:
Since carving out Mini-OS from the Xen repository there hasn't been a
description of t
Dario, Meng,
On 12.02.18 12:17, Dario Faggioli wrote:
Well, I'll let Andrii reply, but honestly, I don't think it is.
See, for instance, the fact that DomR has only 1 vCPU, so I find it
unlikely that the only thing that run there is *just* *one* real-time
task. :-/
While I'm focused mainly on
Hi Andre,
On 09/02/18 14:38, Andre Przywara wrote:
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 5f47aa84a9..2fc6e19625 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -285,7 +285,7 @@ bool vgic_migrate_irq(struct vcpu *old, struct vcpu *new,
unsigned int irq)
Hi Andre,
On 09/02/18 14:38, Andre Przywara wrote:
Currently we describe the VGIC specific fields in an structure
*embedded* in struct arch_domain and struct arch_vcpu. These members
there are however related to the current VGIC implementation, and will
be substantially different in the future.
* Rename some fields for consistency and clarity, and use standard types.
* Don't opencode the use of ALT_{ORIG,REPL}_PTR().
No functional change.
Signed-off-by: Andrew Cooper
---
CC: Jan Beulich
CC: Konrad Rzeszutek Wilk
CC: Roger Pau Monné
CC: Wei Liu
---
xen/arch/x86/alternative.c
ALTERNATIVE_3 is more complicated than ALTERNATIVE_2 when it comes to
calculating extra padding length, and we have no need for the complexity.
Signed-off-by: Andrew Cooper
---
CC: Jan Beulich
CC: Konrad Rzeszutek Wilk
CC: Roger Pau Monné
CC: Wei Liu
---
xen/include/asm-x86/alternative.h | 2
This is the end result of a lot of work I started during the Spectre/Meltdown
embargo window, and deferred because it was taking too long. It finally
resolves the explict padding calculations for the SPEC_CTRL alternatives.
Andrew Cooper (7):
x86/alt: Drop unused alternative infrastructure
x8
With future changes, altinstruction_entry is going to become more complicated
to use. Furthermore, there are already ALTERNATIVE* macros which can be used
to avoid opencoding the creation of replacement information.
For ASM_STAC, ASM_CLAC and CR4_PV32_RESTORE, this means the removal of all
hardoc
On Sun, Feb 11, 2018 at 12:34:11PM +0800, Chao Gao wrote:
> On Fri, Feb 09, 2018 at 04:59:11PM +, Roger Pau Monné wrote:
> >On Fri, Nov 17, 2017 at 02:22:16PM +0800, Chao Gao wrote:
> >> +return;
> >> +
> >> +/*
> >> + * Hardware clears this bit when software sets the SIRTPS fie
Now that the alternatives infrastructure can calculate the required padding
automatically, there is no need to hard code it.
Signed-off-by: Andrew Cooper
---
CC: Jan Beulich
CC: Konrad Rzeszutek Wilk
CC: Roger Pau Monné
CC: Wei Liu
---
xen/arch/x86/x86_64/compat/entry.S | 2 +-
xen/arch/x8
The correct amount of padding in an origin patch site can be calculated
automatically, based on the relative lengths of the replacements.
This requires a bit of trickery to calculate correctly, especially in the
ALTENRATIVE_2 case where a branchless max() calculation in needed. The
calculation is
* On the C side, switch to using local lables rather than hardcoded numbers.
* Rename parameters and lables to be consistent with alt_instr names, and
consistent between the the C and asm versions.
* On the asm side, factor some expressions out into macros to aid clarity.
* Consistently decl
Newer versions of binutils are capable of emitting an exact number bytes worth
of optimised nops. Use this in preference to .skip when available.
Signed-off-by: Andrew Cooper
---
CC: Jan Beulich
CC: Konrad Rzeszutek Wilk
CC: Roger Pau Monné
CC: Wei Liu
RFC until support is actually committe
On Sun, Feb 11, 2018 at 01:05:01PM +0800, Chao Gao wrote:
> On Fri, Feb 09, 2018 at 05:15:17PM +, Roger Pau Monné wrote:
> >On Fri, Nov 17, 2017 at 02:22:17PM +0800, Chao Gao wrote:
> >> +static void write_gcmd_ire(struct vvtd *vvtd, uint32_t val)
> >> +{
> >> +bool set = val & DMA_GCMD_IRE
Changed the error message when trying to map a null size file.
When doing `xl create` command, we get an Invalid Kernel error
when the file size is greater than zero. For zero length files, we are
falling in the mmap error, and we get an `Invalid parameter` error,
which is not explicit. With this c
On 09/02/18 15:06, Andre Przywara wrote:
Hi,
Hi Andre,
On 09/02/18 14:38, Andre Przywara wrote:
tl;dr: More preparatory patches from patch 07, actual new VGIC starting
at patch 20.
=
During development of the Dom0 ITS MSI support last year we realised
that the existing GIC int
Hi Andre,
On 09/02/18 14:38, Andre Przywara wrote:
/*
- * Allocate a guest VIRQ
- * - spi == 0 => allocate a PPI. It will be the same on every vCPU
- * - spi == 1 => allocate an SPI
+ * In the moment vgic_num_irqs() just covers SPIs and the private IRQs,
+ * as it's mostly used for allocatin
Hi,
On 12/02/18 11:48, Julien Grall wrote:
>
>
> On 09/02/18 15:06, Andre Przywara wrote:
>> Hi,
>
> Hi Andre,
>
>> On 09/02/18 14:38, Andre Przywara wrote:
>>> tl;dr: More preparatory patches from patch 07, actual new VGIC starting
>>> at patch 20.
>>> =
>>>
>>> During development
On Fri, Nov 17, 2017 at 02:22:19PM +0800, Chao Gao wrote:
> Without interrupt remapping, interrupt attributes can be extracted from
> msi message or IOAPIC RTE. However, with interrupt remapping enabled,
> the attributes are enclosed in the associated IRTE. This callback is
> for cases in which the
Hi Andre,
On 09/02/18 14:39, Andre Przywara wrote:
So far the number of list registers (LRs) a GIC implements is only
needed in the hardware facing side of the VGIC code (gic-vgic.c).
The new VGIC will need this information in more and multiple places, so
export a function that returns the numbe
Hi,
On 12/02/18 11:15, Julien Grall wrote:
> Hi Andre,
>
> On 09/02/18 14:38, Andre Przywara wrote:
>> diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
>> index 5f47aa84a9..2fc6e19625 100644
>> --- a/xen/arch/arm/vgic.c
>> +++ b/xen/arch/arm/vgic.c
>> @@ -285,7 +285,7 @@ bool vgic_migrate_i
Hi Andre,
On 09/02/18 14:39, Andre Przywara wrote:
The new VGIC will need to know the hypervisor base address at some
point, which is private to the hardware facing part of the VGIC so far.
Add a parameter to vgic_v2_setup_hw() to pass this address on, so a VGIC
implementation can make use of it
On Fri, Nov 17, 2017 at 02:22:20PM +0800, Chao Gao wrote:
> Different platform may use different method to distinguish
> remapping format interrupt and normal format interrupt.
>
> Intel uses one bit in IOAPIC RTE or MSI address register to
> indicate the interrupt is remapping format. vvtd should
On 12/02/18 11:59, Andre Przywara wrote:
Hi,
Hi Andre,
On 12/02/18 11:15, Julien Grall wrote:
Hi Andre,
On 09/02/18 14:38, Andre Przywara wrote:
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 5f47aa84a9..2fc6e19625 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
On Mon, Feb 12, 2018 at 11:23:02AM +, Andrew Cooper wrote:
> * Rename some fields for consistency and clarity, and use standard types.
> * Don't opencode the use of ALT_{ORIG,REPL}_PTR().
And change u8 etc.
>
> No functional change.
>
> Signed-off-by: Andrew Cooper
> ---
> CC: Jan Beulic
On Mon, Feb 12, 2018 at 11:23:04AM +, Andrew Cooper wrote:
> diff --git a/xen/arch/x86/x86_64/entry.S b/xen/arch/x86/x86_64/entry.S
> index 58f652d..bd3819a 100644
> --- a/xen/arch/x86/x86_64/entry.S
> +++ b/xen/arch/x86/x86_64/entry.S
> @@ -557,23 +557,9 @@ handle_exception_saved:
> t
On Mon, Feb 12, 2018 at 11:23:03AM +, Andrew Cooper wrote:
> * On the C side, switch to using local lables rather than hardcoded numbers.
> * Rename parameters and lables to be consistent with alt_instr names, and
>consistent between the the C and asm versions.
> * On the asm side, facto
On Mon, Feb 12, 2018 at 11:23:01AM +, Andrew Cooper wrote:
> ALTERNATIVE_3 is more complicated than ALTERNATIVE_2 when it comes to
> calculating extra padding length, and we have no need for the complexity.
>
> Signed-off-by: Andrew Cooper
Reviewed-by: Wei Liu
_
Hi,
This patch seem to modify the GICv2 CPU interface definitions. If so,
please make it clear in the commit message/title.
On 09/02/18 14:39, Andre Przywara wrote:
The new VGIC will shortly use more bits of the GICC_CTLR register, so
add the respective definitions from the manual.
Also add a
On 12/02/18 12:30, Wei Liu wrote:
> On Mon, Feb 12, 2018 at 11:23:04AM +, Andrew Cooper wrote:
>> diff --git a/xen/arch/x86/x86_64/entry.S b/xen/arch/x86/x86_64/entry.S
>> index 58f652d..bd3819a 100644
>> --- a/xen/arch/x86/x86_64/entry.S
>> +++ b/xen/arch/x86/x86_64/entry.S
>> @@ -557,23 +557,
On Mon, Feb 12, 2018 at 01:09:15PM +0100, Paul Semel wrote:
> Changed the error message when trying to map a null size file.
> When doing `xl create` command, we get an Invalid Kernel error
> when the file size is greater than zero. For zero length files, we are
> falling in the mmap error, and we
Hi all,
I am working in a project in which we try to switch domain's underlying
machine memory(MFNs) for another "chunk" of the same size while the VM is
running. This can be useful for example when a domain running a memory
intensive load experiences performance penalties(e.g: lot of cache misses
On Mon, Feb 12, 2018 at 11:23:04AM +, Andrew Cooper wrote:
> With future changes, altinstruction_entry is going to become more complicated
> to use. Furthermore, there are already ALTERNATIVE* macros which can be used
> to avoid opencoding the creation of replacement information.
>
> For ASM_
On Fri, Nov 17, 2017 at 02:22:21PM +0800, Chao Gao wrote:
> Interrupt translation faults are non-recoverable fault. When faults
> are triggered, it needs to populate fault info to Fault Recording
> Registers and inject msi interrupt to notify guest IOMMU driver
> to deal with faults.
>
> This patc
branch xen-unstable
xenbranch xen-unstable
job test-amd64-i386-xl-xsm
testid xen-boot
Tree: linux git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
Tree: linuxfirmware git://xenbits.xen.org/osstest/linux-firmware.git
Tree: qemu git://xenbits.xen.org/qemu-xen-traditional.git
Tree
On 05/02/18 23:51, Stefano Stabellini wrote:
> Introduce a per sock_mapping refcount, in addition to the existing
> global refcount. Thanks to the sock_mapping refcount, we can safely wait
> for it to be 1 in pvcalls_front_release before freeing an active socket,
> instead of waiting for the global
On 05/02/18 23:51, Stefano Stabellini wrote:
> Passive sockets can have ongoing operations on them, specifically, we
> have two wait_event_interruptable calls in pvcalls_front_accept.
>
> Add two wake_up calls in pvcalls_front_release, then wait for the
> potential waiters to return and release th
On 02/02/18 18:42, Joao Martins wrote:
> Commit fd8aa9095a95 ("xen: optimize xenbus driver for multiple concurrent
> xenstore accesses") optimized xenbus concurrent accesses but in doing so
> broke UABI of /dev/xen/xenbus. Through /dev/xen/xenbus applications are in
> charge of xenbus message excha
On 08/02/18 00:49, Prarit Bhargava wrote:
> The kernel panics on PV domains because native_smp_cpus_done() is
> only called for HVM domains.
>
> Calculate __max_logical_packages for PV domains.
>
> Fixes: b4c0a7326f5d ("x86/smpboot: Fix __max_logical_packages estimate")
> Signed-off-by: Prarit Bh
Hi Andre,
On 09/02/18 14:39, Andre Przywara wrote:
When playing around with hardware mapped, level triggered virtual IRQs,
there is the need to explicitly set the active state of an interrupt at
some point in time.
To prepare the GIC for that, we introduce a set_active_state() function
to let th
Hi Andre,
On 09/02/18 14:39, Andre Przywara wrote:
To synchronize level triggered interrupts which are mapped into a guest,
we need to update the virtual line level at certain points in time.
For a hardware mapped interrupt the GIC is the only place where we can
easily access this information.
I
flight 118995 xen-unstable-smoke real [real]
http://logs.test-lab.xenproject.org/osstest/logs/118995/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-amd64-amd64-libvirt 13 migrate-support-checkfail never pass
test-arm64-arm64-xl-xsm 1
On Fri, Nov 17, 2017 at 02:22:22PM +0800, Chao Gao wrote:
> Software writes to QIE field of GCMD to enable or disable queued
> invalidations. This patch emulates QIE field of GCMD.
>
> Signed-off-by: Chao Gao
> Signed-off-by: Lan Tianyu
> ---
> xen/drivers/passthrough/vtd/iommu.h | 3 ++-
> xe
Hi,
On 12/02/18 12:19, Julien Grall wrote:
>
>
> On 12/02/18 11:59, Andre Przywara wrote:
>> Hi,
>
> Hi Andre,
>
>> On 12/02/18 11:15, Julien Grall wrote:
>>> Hi Andre,
>>>
>>> On 09/02/18 14:38, Andre Przywara wrote:
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 5f47a
On Fri, Nov 17, 2017 at 02:22:23PM +0800, Chao Gao wrote:
> Queued Invalidation Interface is an expanded invalidation interface with
> extended capabilities. Hardware implementations report support for queued
> invalidation interface through the Extended Capability Register. The queued
> invalidati
On Mon, Feb 12, 2018 at 11:23:05AM +, Andrew Cooper wrote:
> The correct amount of padding in an origin patch site can be calculated
> automatically, based on the relative lengths of the replacements.
>
> This requires a bit of trickery to calculate correctly, especially in the
> ALTENRATIVE_2
On Mon, Feb 12, 2018 at 11:23:07AM +, Andrew Cooper wrote:
> Newer versions of binutils are capable of emitting an exact number bytes worth
> of optimised nops. Use this in preference to .skip when available.
>
> Signed-off-by: Andrew Cooper
Reviewed-by: Wei Liu
__
On Mon, Feb 12, 2018 at 11:23:06AM +, Andrew Cooper wrote:
> Now that the alternatives infrastructure can calculate the required padding
> automatically, there is no need to hard code it.
>
> Signed-off-by: Andrew Cooper
Reviewed-by: Wei Liu
___
On Mon, Feb 12, 2018 at 09:27:25AM +0100, Yessine Daoud wrote:
> Hello,
>
> Thank you for your quick response.
> Any hints how can I "fix" this "issue"? *Any workaround?
>
Honestly I have no idea why it is slow unless there is more logging
available.
Wei.
_
On Thu, Feb 08, 2018 at 07:21:50PM +, Julien Grall wrote:
> At the moment, Xen provides virtual PSCI interface compliant with 0.1
> and 0.2. Since them, the specification has been updated and the latest
> version is 1.1 (see ARM DEN 0022D).
>
> From an implementation point of view, only PSCI_F
Hi Julien,
On 09.02.18 19:09, Julien Grall wrote:
On 02/09/2018 05:04 PM, Volodymyr Babchuk wrote:
Julien,
On 08.02.18 21:21, Julien Grall wrote:
PSCI 1.0 and later allows the SMCCC version to be (indirectly) probed
via PSCI_FEATURES. If the PSCI_FEATURES does not exist (PSCI 0.2 or
earlie
On Thu, Feb 08, 2018 at 08:10:50PM -0700, Sameer Goel wrote:
> Changing the name of the macro from LOG_2 to ilog2.This makes the function
> name
> similar to its Linux counterpart. Since, this is not used in multiple places,
> the code churn is minimal.
>
> This change helps in porting unchanged
On Fri, Nov 17, 2017 at 02:22:24PM +0800, Chao Gao wrote:
> Provide a save-restore pair to save/restore registers and non-register
> status.
>
> Signed-off-by: Chao Gao
> Signed-off-by: Lan Tianyu
> ---
> v3:
> - use one entry to save both vvtd registers and other intermediate
> state
> ---
>
On Thu, Feb 08, 2018 at 08:10:49PM -0700, Sameer Goel wrote:
>
> +#define WARN_ON_ONCE(p) \
> +({ \
> +static bool __section(".data.unlikely") __warned; \
> +int __ret_warn_once = !!(p);\
> +
On Thu, Feb 08, 2018 at 10:49:07PM +0100, Simon Gaiser wrote:
> Simon Gaiser (3):
> libxc: Cleanup xc_dom_parse_elf_kernel()'s return value
> libxl: Improve logging in libxl__build_dom()
> libxc: xc_dom_parse_elf_kernel: Return error for invalid kernel images
Acked-by: Wei Liu
Hi Julien an Wei,
2018-02-08 0:54 GMT+08:00 Julien Grall :
> On 07/02/18 16:27, Zhongze Liu wrote:
>>
>> Hi Wei and Julien,
>
>
> Hi,
>
>
>> 2018-02-07 2:06 GMT+08:00 Wei Liu :
>>>
>>> On Tue, Feb 06, 2018 at 01:24:30PM +, Julien Grall wrote:
>
>if (libxl__device_pci_destroy_al
On Mon, Feb 12, 2018 at 6:08 AM, Andrii Anisov wrote:
>
> Dario, Meng,
>
>
> On 12.02.18 12:17, Dario Faggioli wrote:
>>
>> Well, I'll let Andrii reply, but honestly, I don't think it is.
>>
>> See, for instance, the fact that DomR has only 1 vCPU, so I find it
>> unlikely that the only thing that
On Fri, Nov 17, 2017 at 02:22:25PM +0800, Chao Gao wrote:
> When irq remapping is enabled, IOAPIC Redirection Entry may be in remapping
> format. If that, generate an irq_remapping_request and call the common
"If that's the case, ..."
> VIOMMU abstraction's callback to handle this interrupt reque
On Fri, Feb 09, 2018 at 09:20:33AM +, Christian Lindig wrote:
>
>
> > On 8. Feb 2018, at 18:24, Wei Liu wrote:
> >
> > Christian, do you have any idea when you can look into fixing the
> > safe-string patch?
>
> Sorry, I can’t make a promise because of my other obligations. I do wonder,
>
On Fri, Nov 17, 2017 at 02:22:26PM +0800, Chao Gao wrote:
> When IOAPIC RTE is in remapping format, it doesn't contain the vector of
> interrupt. For this case, the RTE contains an index of interrupt remapping
> table where the vector of interrupt is stored. This patchs gets the vector
> through a
On 12/02/18 14:39, Wei Liu wrote:
> On Mon, Feb 12, 2018 at 11:23:05AM +, Andrew Cooper wrote:
>> The correct amount of padding in an origin patch site can be calculated
>> automatically, based on the relative lengths of the replacements.
>>
>> This requires a bit of trickery to calculate corre
On 12/02/18 14:43, Volodymyr Babchuk wrote:
Hi Julien,
On 09.02.18 19:09, Julien Grall wrote:
On 02/09/2018 05:04 PM, Volodymyr Babchuk wrote:
Julien,
On 08.02.18 21:21, Julien Grall wrote:
PSCI 1.0 and later allows the SMCCC version to be (indirectly) probed
via PSCI_FEATURES. If the P
Hi Wei and Julien,
2018-02-07 1:47 GMT+08:00 Wei Liu :
> On Tue, Feb 06, 2018 at 05:30:50PM +, Julien Grall wrote:
>>
>>
>> On 02/06/2018 03:59 PM, Zhongze Liu wrote:
>> > Hi Julien,
>>
>> Hi,
>>
>>
>> > 2018-02-06 21:07 GMT+08:00 Julien Grall :
>> > > Hi,
>> > >
>> > > On 01/30/2018 05:50 PM,
This commit implements the breakpoint events for svm.
At the moment, the Breakpoint vmexit is not forwarded to the monitor layer.
This patch adds the hvm_monitor_debug call to the VMEXIT_EXCEPTION_BP.
Also, the Software Breakpoint cap is moved from the Intel arch to the
common part of the code.
Si
Hi all,
This series provides a skeleton for enabling vm_events on SVM. For the
first step, the MSR, CR, Breakpoint and GuestRequest have been tested
and added to the capabilities list.
Cheers,
Alexandru Isaila
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The CR_INTERCEPT_CR3_WRITE intercept is out of the vmcb->_cr_intercepts
so the AMD arch can't intercept CR events.
This patch implements the CR intercept by adding the flag on a
write_ctrlreg event. The monitor write ctrlreg event is moved from the
Intel side to the common capabilities side.
We j
At this moment there is no function to enable msr interception on svm.
This patch implements this function and moves the mov to msr monitor event
form the Intel arch side to the common capabilities.
Signed-off-by: Alexandru Isaila
Acked-by: Tamas K Lengyel
Reviewed-by: Boris Ostrovsky
---
xen
No monitor features are available on AMD and all
capabilities are passed only to the Intel processor architecture.
This means that the arch_monitor_get_capabilities returns
capabilities = 0.
This patch is separating out features which are implemented on both
systems from those implemented only on
Hi,
On 12/02/18 14:52, Zhongze Liu wrote:
2018-02-08 0:54 GMT+08:00 Julien Grall :
On 07/02/18 16:27, Zhongze Liu wrote:
It seems that I mistakenly use transaction as a global lock. Now I don't have
any reasons not putting the unmap out of the transaction, but this will break
the original tran
Hi Julien,
2018-02-12 23:09 GMT+08:00 Julien Grall :
> Hi,
>
> On 12/02/18 14:52, Zhongze Liu wrote:
>>
>> 2018-02-08 0:54 GMT+08:00 Julien Grall :
>>>
>>> On 07/02/18 16:27, Zhongze Liu wrote:
>>
>> It seems that I mistakenly use transaction as a global lock. Now I don't
>> have
>> any reasons no
On 12/02/18 15:08, Alexandru Isaila wrote:
> No monitor features are available on AMD and all
> capabilities are passed only to the Intel processor architecture.
> This means that the arch_monitor_get_capabilities returns
> capabilities = 0.
>
> This patch is separating out features which are imple
On Fri, Nov 17, 2017 at 02:22:27PM +0800, Chao Gao wrote:
> ... rather than a filtered one. Previously, some fields (reserved or
> unalterable) are filtered by QEMU. These fields are useless for the
> legacy interrupt format (i.e. non remappable format). However, these
> fields are meaningful to re
Hi Andre,
On 09/02/18 14:39, Andre Przywara wrote:
The ARM Generic Timer uses a level-sensitive interrupt semantic. We
easily catch when the line goes high, as this triggers the hardware IRQ.
However we have to sync the state of the interrupt condition at certain
points to catch when the line go
On 12/02/18 15:17, Zhongze Liu wrote:
Hi Julien,
Hi,
2018-02-12 23:09 GMT+08:00 Julien Grall :
Hi,
On 12/02/18 14:52, Zhongze Liu wrote:
2018-02-08 0:54 GMT+08:00 Julien Grall :
On 07/02/18 16:27, Zhongze Liu wrote:
It seems that I mistakenly use transaction as a global lock. Now I
On Fri, Nov 17, 2017 at 02:22:28PM +0800, Chao Gao wrote:
> ... handlding guest's invalidation request.
>
> To support pirq migration optimization and using VT-d posted interrupt to
> inject msi from assigned devices, each time guest programs msi information
> (affinity, vector), the struct hvm_gm
On Mon, Feb 12, 2018 at 8:08 AM, Alexandru Isaila
wrote:
> This commit implements the breakpoint events for svm.
> At the moment, the Breakpoint vmexit is not forwarded to the monitor layer.
This is a bit confusing as it sounds like as if you were saying that
after this patch the event is not for
On 12/02/18 15:08, Alexandru Isaila wrote:
> @@ -2619,14 +2634,31 @@ void svm_vmexit_handler(struct cpu_user_regs *regs)
> break;
>
> case VMEXIT_EXCEPTION_BP:
> -if ( !v->domain->debugger_attached )
> -goto unexpected_exit_type;
> -/* AMD Vol2, 15.11: IN
On Mon, Feb 12, 2018 at 11:23:01AM +, Andrew Cooper wrote:
> ALTERNATIVE_3 is more complicated than ALTERNATIVE_2 when it comes to
> calculating extra padding length, and we have no need for the complexity.
>
> Signed-off-by: Andrew Cooper
Reviewed-by: Roger Pau Monné
I guess you also don'
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