Re: [Xen-devel] [PATCH] x86/boot: Disable IBRS in intr/nmi exit path at bootup stage

[Zhenzhong Duan]

在 2018/3/26 21:39, Jan Beulich 写道:

On 21.03.18 at 03:58,  wrote:

After reset, IBRS is disabled by processor, but a coming intr/nmi leave IBRS
enabled after their exit. It's not necessory for bootup code to run in low
performance with IBRS enabled.

On ORACLE X6-2(500GB/88 cpus, dom0 11GB/20 vcpus), we observed an 200s+ delay
in construct_dom0.

By initializing use_shadow_spec_ctrl with 1, IBRS is disabled in intr/nmi exit
path at bootup stage. Then delay in construct_dom0 is ~50s.


While I can certainly follow the argumentation, did you pay
attention to Andrew also modifying what you would call "bootup
code" in commit 7c508612f7 ("x86: Support indirect thunks from
assembly code")? That wasn't just a random change - we
specifically want it for the case of bringing up CPUs at runtime.
You'll need to be equally careful here, I think: Rather than
storing literal 1 (which should have been "true" anyway), you'll
want to store (system_state < SYS_STATE_active) or maybe
(system_state != SYS_STATE_active), at least when the CPU
being booted is a hyperthread of a CPU which is active already.

Make sense for me, thank you for explanation. I'll send a new patch.

Regards
Zhenzhong

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Re: [Xen-devel] [PATCH] x86/boot: Disable IBRS in intr/nmi exit path at bootup stage

[Jan Beulich]

>>> On 21.03.18 at 03:58,  wrote:
> After reset, IBRS is disabled by processor, but a coming intr/nmi leave IBRS
> enabled after their exit. It's not necessory for bootup code to run in low
> performance with IBRS enabled.
> 
> On ORACLE X6-2(500GB/88 cpus, dom0 11GB/20 vcpus), we observed an 200s+ delay
> in construct_dom0.
> 
> By initializing use_shadow_spec_ctrl with 1, IBRS is disabled in intr/nmi exit
> path at bootup stage. Then delay in construct_dom0 is ~50s.

While I can certainly follow the argumentation, did you pay
attention to Andrew also modifying what you would call "bootup
code" in commit 7c508612f7 ("x86: Support indirect thunks from
assembly code")? That wasn't just a random change - we
specifically want it for the case of bringing up CPUs at runtime.
You'll need to be equally careful here, I think: Rather than
storing literal 1 (which should have been "true" anyway), you'll
want to store (system_state < SYS_STATE_active) or maybe
(system_state != SYS_STATE_active), at least when the CPU
being booted is a hyperthread of a CPU which is active already.

Jan


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[Xen-devel] [PATCH] x86/boot: Disable IBRS in intr/nmi exit path at bootup stage

[Zhenzhong Duan]

After reset, IBRS is disabled by processor, but a coming intr/nmi leave IBRS
enabled after their exit. It's not necessory for bootup code to run in low
performance with IBRS enabled.

On ORACLE X6-2(500GB/88 cpus, dom0 11GB/20 vcpus), we observed an 200s+ delay
in construct_dom0.

By initializing use_shadow_spec_ctrl with 1, IBRS is disabled in intr/nmi exit
path at bootup stage. Then delay in construct_dom0 is ~50s.

Signed-off-by: Zhenzhong Duan 
---
 xen/include/asm-x86/spec_ctrl.h |3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/xen/include/asm-x86/spec_ctrl.h b/xen/include/asm-x86/spec_ctrl.h
index 5ab4ff3..c619a80 100644
--- a/xen/include/asm-x86/spec_ctrl.h
+++ b/xen/include/asm-x86/spec_ctrl.h
@@ -33,7 +33,8 @@ static inline void init_shadow_spec_ctrl_state(void)
 {
 struct cpu_info *info = get_cpu_info();
 
-info->shadow_spec_ctrl = info->use_shadow_spec_ctrl = 0;
+info->shadow_spec_ctrl = 0;
+info->use_shadow_spec_ctrl = 1;
 info->bti_ist_info = default_bti_ist_info;
 }
 
-- 
1.7.3

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