Re: [Xen-devel] [PATCH 09/12] Expose ich_read/write_lr in vsysreg_errata.c

2018-03-13 Thread Julien Grall 



On 12/03/18 12:42, mja...@caviumnetworks.com wrote:

From: Manish Jaggi 

gicv3_ich_read/write_lr functions are duplicated in vsysreg_errata.c


Please explain the rationale. I.e we want to have the workaround standalone.

Cheers,



Signed-off-by: Manish Jaggi 
---
  xen/arch/arm/arm64/vsysreg_errata.c | 83 +
  1 file changed, 83 insertions(+)

diff --git a/xen/arch/arm/arm64/vsysreg_errata.c 
b/xen/arch/arm/arm64/vsysreg_errata.c
index b2a95a69dc..d7bf9d6ce3 100644
--- a/xen/arch/arm/arm64/vsysreg_errata.c
+++ b/xen/arch/arm/arm64/vsysreg_errata.c
@@ -189,6 +189,89 @@ u32  __vgic_v3_read_ap1rn(int n)
  return val;
  }
  
+static uint64_t gicv3_ich_read_lr(int lr)

+{
+switch ( lr )
+{
+case 0: return READ_SYSREG(ICH_LR0_EL2);
+case 1: return READ_SYSREG(ICH_LR1_EL2);
+case 2: return READ_SYSREG(ICH_LR2_EL2);
+case 3: return READ_SYSREG(ICH_LR3_EL2);
+case 4: return READ_SYSREG(ICH_LR4_EL2);
+case 5: return READ_SYSREG(ICH_LR5_EL2);
+case 6: return READ_SYSREG(ICH_LR6_EL2);
+case 7: return READ_SYSREG(ICH_LR7_EL2);
+case 8: return READ_SYSREG(ICH_LR8_EL2);
+case 9: return READ_SYSREG(ICH_LR9_EL2);
+case 10: return READ_SYSREG(ICH_LR10_EL2);
+case 11: return READ_SYSREG(ICH_LR11_EL2);
+case 12: return READ_SYSREG(ICH_LR12_EL2);
+case 13: return READ_SYSREG(ICH_LR13_EL2);
+case 14: return READ_SYSREG(ICH_LR14_EL2);
+case 15: return READ_SYSREG(ICH_LR15_EL2);
+default:
+BUG();
+}
+}
+
+static void gicv3_ich_write_lr(int lr, uint64_t val)
+{
+switch ( lr )
+{
+case 0:
+WRITE_SYSREG(val, ICH_LR0_EL2);
+break;
+case 1:
+WRITE_SYSREG(val, ICH_LR1_EL2);
+break;
+case 2:
+WRITE_SYSREG(val, ICH_LR2_EL2);
+break;
+case 3:
+WRITE_SYSREG(val, ICH_LR3_EL2);
+break;
+case 4:
+WRITE_SYSREG(val, ICH_LR4_EL2);
+break;
+case 5:
+WRITE_SYSREG(val, ICH_LR5_EL2);
+break;
+case 6:
+WRITE_SYSREG(val, ICH_LR6_EL2);
+break;
+case 7:
+WRITE_SYSREG(val, ICH_LR7_EL2);
+break;
+case 8:
+WRITE_SYSREG(val, ICH_LR8_EL2);
+break;
+case 9:
+WRITE_SYSREG(val, ICH_LR9_EL2);
+break;
+case 10:
+WRITE_SYSREG(val, ICH_LR10_EL2);
+break;
+case 11:
+WRITE_SYSREG(val, ICH_LR11_EL2);
+break;
+case 12:
+WRITE_SYSREG(val, ICH_LR12_EL2);
+break;
+case 13:
+WRITE_SYSREG(val, ICH_LR13_EL2);
+break;
+case 14:
+WRITE_SYSREG(val, ICH_LR14_EL2);
+break;
+case 15:
+WRITE_SYSREG(val, ICH_LR15_EL2);
+break;
+default:
+return;
+}
+isb();
+}
+
  bool vgic_v3_handle_cpuif_access(struct cpu_user_regs *regs, const union hsr 
hsr)
  {
  bool ret = 0;



--
Julien Grall

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[Xen-devel] [PATCH 09/12] Expose ich_read/write_lr in vsysreg_errata.c

2018-03-12 Thread mjaggi 
From: Manish Jaggi 

gicv3_ich_read/write_lr functions are duplicated in vsysreg_errata.c

Signed-off-by: Manish Jaggi 
---
 xen/arch/arm/arm64/vsysreg_errata.c | 83 +
 1 file changed, 83 insertions(+)

diff --git a/xen/arch/arm/arm64/vsysreg_errata.c 
b/xen/arch/arm/arm64/vsysreg_errata.c
index b2a95a69dc..d7bf9d6ce3 100644
--- a/xen/arch/arm/arm64/vsysreg_errata.c
+++ b/xen/arch/arm/arm64/vsysreg_errata.c
@@ -189,6 +189,89 @@ u32  __vgic_v3_read_ap1rn(int n)
 return val;
 }
 
+static uint64_t gicv3_ich_read_lr(int lr)
+{
+switch ( lr )
+{
+case 0: return READ_SYSREG(ICH_LR0_EL2);
+case 1: return READ_SYSREG(ICH_LR1_EL2);
+case 2: return READ_SYSREG(ICH_LR2_EL2);
+case 3: return READ_SYSREG(ICH_LR3_EL2);
+case 4: return READ_SYSREG(ICH_LR4_EL2);
+case 5: return READ_SYSREG(ICH_LR5_EL2);
+case 6: return READ_SYSREG(ICH_LR6_EL2);
+case 7: return READ_SYSREG(ICH_LR7_EL2);
+case 8: return READ_SYSREG(ICH_LR8_EL2);
+case 9: return READ_SYSREG(ICH_LR9_EL2);
+case 10: return READ_SYSREG(ICH_LR10_EL2);
+case 11: return READ_SYSREG(ICH_LR11_EL2);
+case 12: return READ_SYSREG(ICH_LR12_EL2);
+case 13: return READ_SYSREG(ICH_LR13_EL2);
+case 14: return READ_SYSREG(ICH_LR14_EL2);
+case 15: return READ_SYSREG(ICH_LR15_EL2);
+default:
+BUG();
+}
+}
+
+static void gicv3_ich_write_lr(int lr, uint64_t val)
+{
+switch ( lr )
+{
+case 0:
+WRITE_SYSREG(val, ICH_LR0_EL2);
+break;
+case 1:
+WRITE_SYSREG(val, ICH_LR1_EL2);
+break;
+case 2:
+WRITE_SYSREG(val, ICH_LR2_EL2);
+break;
+case 3:
+WRITE_SYSREG(val, ICH_LR3_EL2);
+break;
+case 4:
+WRITE_SYSREG(val, ICH_LR4_EL2);
+break;
+case 5:
+WRITE_SYSREG(val, ICH_LR5_EL2);
+break;
+case 6:
+WRITE_SYSREG(val, ICH_LR6_EL2);
+break;
+case 7:
+WRITE_SYSREG(val, ICH_LR7_EL2);
+break;
+case 8:
+WRITE_SYSREG(val, ICH_LR8_EL2);
+break;
+case 9:
+WRITE_SYSREG(val, ICH_LR9_EL2);
+break;
+case 10:
+WRITE_SYSREG(val, ICH_LR10_EL2);
+break;
+case 11:
+WRITE_SYSREG(val, ICH_LR11_EL2);
+break;
+case 12:
+WRITE_SYSREG(val, ICH_LR12_EL2);
+break;
+case 13:
+WRITE_SYSREG(val, ICH_LR13_EL2);
+break;
+case 14:
+WRITE_SYSREG(val, ICH_LR14_EL2);
+break;
+case 15:
+WRITE_SYSREG(val, ICH_LR15_EL2);
+break;
+default:
+return;
+}
+isb();
+}
+
 bool vgic_v3_handle_cpuif_access(struct cpu_user_regs *regs, const union hsr 
hsr)
 {
 bool ret = 0;
-- 
2.14.1


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