Re: [Xen-devel] [PATCH v3 13/17] x86/xen: enable Hygon support to Xen
On 08/16/2018 09:29 AM, Pu Wen wrote:
> On 2018/8/12 21:26, Boris Ostrovsky wrote:
>> On 08/12/2018 04:55 AM, Juergen Gross wrote:
>>> On 11/08/18 16:34, Boris Ostrovsky wrote:
On 08/11/2018 09:29 AM, Pu Wen wrote:
> bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err)
> {
> - if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
> + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
> + boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
'if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)' please.
>>> Really? Xen supports Centaur, too.
>>
>> VPMU doesn't --- hypervisor will not initialize it. Besides, the
>> existing code will steer non-AMD execution to Intel, which is not right
>> either.
>>
>> I'll add a check to bail if VPMU is not initialized properly, we seem to
>> ignore xen_pmu_init() failures. Which, BTW, makes this patch rather
>> pointless until there is support for Hygon Xen.
>
> So should it still need to test vendor Hygon here or wait for your check
> done?
I'd prefer checking for !Intel, as I suggested above. Centaur will fail
either way, but because we use safe versions of MSR access I now think
we don't need any extra checks for xen_pmu_init() result.
-boris
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Re: [Xen-devel] [PATCH v3 13/17] x86/xen: enable Hygon support to Xen
On 2018/8/12 21:26, Boris Ostrovsky wrote:
On 08/12/2018 04:55 AM, Juergen Gross wrote:
On 11/08/18 16:34, Boris Ostrovsky wrote:
On 08/11/2018 09:29 AM, Pu Wen wrote:
bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err)
{
- if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
+ boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
'if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)' please.
Really? Xen supports Centaur, too.
VPMU doesn't --- hypervisor will not initialize it. Besides, the
existing code will steer non-AMD execution to Intel, which is not right
either.
I'll add a check to bail if VPMU is not initialized properly, we seem to
ignore xen_pmu_init() failures. Which, BTW, makes this patch rather
pointless until there is support for Hygon Xen.
So should it still need to test vendor Hygon here or wait for your check
done?
Thanks,
Pu Wen
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Re: [Xen-devel] [PATCH v3 13/17] x86/xen: enable Hygon support to Xen
On 2018/8/11 22:34, Boris Ostrovsky wrote:
On 08/11/2018 09:29 AM, Pu Wen wrote:
To make Xen work correctly on Hygon platforms, reuse AMD's Xen support
code path and add vendor check for Hygon along with AMD.
Signed-off-by: Pu Wen
---
arch/x86/xen/pmu.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c
index 7d00d4a..1053dda 100644
--- a/arch/x86/xen/pmu.c
+++ b/arch/x86/xen/pmu.c
@@ -90,6 +90,12 @@ static void xen_pmu_arch_init(void)
k7_counters_mirrored = 0;
break;
}
+ } else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
+ amd_num_counters = F10H_NUM_COUNTERS;
I haven't looked in details at Zen's PMU but the PMC section in the spec
starts with
"There are six core performance events counters per thread..."
There are six core performance events counters per thread, so there are
six MSRs for these counters(0-5). Also there are four legacy PMC MSRs,
they are alias of the counters(0-3).
In this version of kernel Zen use the lagacy version of PMU MSRs for Xen.
For safety consideration, Dhyana just fullow this stategy. And it works
fine when VPMU enabled in Xen on Hygon platforms by testing with perf.
Thanks,
Pu Wen
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Re: [Xen-devel] [PATCH v3 13/17] x86/xen: enable Hygon support to Xen
On 08/12/2018 04:55 AM, Juergen Gross wrote:
> On 11/08/18 16:34, Boris Ostrovsky wrote:
>> On 08/11/2018 09:29 AM, Pu Wen wrote:
>>
>>>
>>> bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err)
>>> {
>>> - if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
>>> + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
>>> + boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
>>
>> 'if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)' please.
> Really? Xen supports Centaur, too.
VPMU doesn't --- hypervisor will not initialize it. Besides, the
existing code will steer non-AMD execution to Intel, which is not right
either.
I'll add a check to bail if VPMU is not initialized properly, we seem to
ignore xen_pmu_init() failures. Which, BTW, makes this patch rather
pointless until there is support for Hygon Xen.
-boris
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Re: [Xen-devel] [PATCH v3 13/17] x86/xen: enable Hygon support to Xen
On 11/08/18 16:34, Boris Ostrovsky wrote:
> On 08/11/2018 09:29 AM, Pu Wen wrote:
>> To make Xen work correctly on Hygon platforms, reuse AMD's Xen support
>> code path and add vendor check for Hygon along with AMD.
>>
>> Signed-off-by: Pu Wen
>> ---
>> arch/x86/xen/pmu.c | 15 ---
>> 1 file changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c
>> index 7d00d4a..1053dda 100644
>> --- a/arch/x86/xen/pmu.c
>> +++ b/arch/x86/xen/pmu.c
>> @@ -90,6 +90,12 @@ static void xen_pmu_arch_init(void)
>> k7_counters_mirrored = 0;
>> break;
>> }
>> +} else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
>> +amd_num_counters = F10H_NUM_COUNTERS;
>
> I haven't looked in details at Zen's PMU but the PMC section in the spec
> starts with
> "There are six core performance events counters per thread..."
>
>
>
>> +amd_counters_base = MSR_K7_PERFCTR0;
>> +amd_ctrls_base = MSR_K7_EVNTSEL0;
>> +amd_msr_step = 1;
>> +k7_counters_mirrored = 0;
>> } else {
>> uint32_t eax, ebx, ecx, edx;
>>
>> @@ -285,7 +291,8 @@ static bool xen_amd_pmu_emulate(unsigned int msr, u64
>> *val, bool is_read)
>>
>> bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err)
>> {
>> -if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
>> +if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
>> +boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
>
>
> 'if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)' please.
Really? Xen supports Centaur, too.
Juergen
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Re: [Xen-devel] [PATCH v3 13/17] x86/xen: enable Hygon support to Xen
On 08/11/2018 09:29 AM, Pu Wen wrote:
> To make Xen work correctly on Hygon platforms, reuse AMD's Xen support
> code path and add vendor check for Hygon along with AMD.
>
> Signed-off-by: Pu Wen
> ---
> arch/x86/xen/pmu.c | 15 ---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c
> index 7d00d4a..1053dda 100644
> --- a/arch/x86/xen/pmu.c
> +++ b/arch/x86/xen/pmu.c
> @@ -90,6 +90,12 @@ static void xen_pmu_arch_init(void)
> k7_counters_mirrored = 0;
> break;
> }
> + } else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
> + amd_num_counters = F10H_NUM_COUNTERS;
I haven't looked in details at Zen's PMU but the PMC section in the spec
starts with
"There are six core performance events counters per thread..."
> + amd_counters_base = MSR_K7_PERFCTR0;
> + amd_ctrls_base = MSR_K7_EVNTSEL0;
> + amd_msr_step = 1;
> + k7_counters_mirrored = 0;
> } else {
> uint32_t eax, ebx, ecx, edx;
>
> @@ -285,7 +291,8 @@ static bool xen_amd_pmu_emulate(unsigned int msr, u64
> *val, bool is_read)
>
> bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err)
> {
> - if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
> + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
> + boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
'if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)' please.
-boris
> if (is_amd_pmu_msr(msr)) {
> if (!xen_amd_pmu_emulate(msr, val, 1))
> *val = native_read_msr_safe(msr, err);
> @@ -308,7 +315,8 @@ bool pmu_msr_write(unsigned int msr, uint32_t low,
> uint32_t high, int *err)
> {
> uint64_t val = ((uint64_t)high << 32) | low;
>
> - if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
> + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
> + boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
> if (is_amd_pmu_msr(msr)) {
> if (!xen_amd_pmu_emulate(msr, &val, 0))
> *err = native_write_msr_safe(msr, low, high);
> @@ -379,7 +387,8 @@ static unsigned long long xen_intel_read_pmc(int counter)
>
> unsigned long long xen_read_pmc(int counter)
> {
> - if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
> + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
> + boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
> return xen_amd_read_pmc(counter);
> else
> return xen_intel_read_pmc(counter);
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[Xen-devel] [PATCH v3 13/17] x86/xen: enable Hygon support to Xen
To make Xen work correctly on Hygon platforms, reuse AMD's Xen support
code path and add vendor check for Hygon along with AMD.
Signed-off-by: Pu Wen
---
arch/x86/xen/pmu.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c
index 7d00d4a..1053dda 100644
--- a/arch/x86/xen/pmu.c
+++ b/arch/x86/xen/pmu.c
@@ -90,6 +90,12 @@ static void xen_pmu_arch_init(void)
k7_counters_mirrored = 0;
break;
}
+ } else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
+ amd_num_counters = F10H_NUM_COUNTERS;
+ amd_counters_base = MSR_K7_PERFCTR0;
+ amd_ctrls_base = MSR_K7_EVNTSEL0;
+ amd_msr_step = 1;
+ k7_counters_mirrored = 0;
} else {
uint32_t eax, ebx, ecx, edx;
@@ -285,7 +291,8 @@ static bool xen_amd_pmu_emulate(unsigned int msr, u64 *val,
bool is_read)
bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err)
{
- if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
+ boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
if (is_amd_pmu_msr(msr)) {
if (!xen_amd_pmu_emulate(msr, val, 1))
*val = native_read_msr_safe(msr, err);
@@ -308,7 +315,8 @@ bool pmu_msr_write(unsigned int msr, uint32_t low, uint32_t
high, int *err)
{
uint64_t val = ((uint64_t)high << 32) | low;
- if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
+ boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
if (is_amd_pmu_msr(msr)) {
if (!xen_amd_pmu_emulate(msr, &val, 0))
*err = native_write_msr_safe(msr, low, high);
@@ -379,7 +387,8 @@ static unsigned long long xen_intel_read_pmc(int counter)
unsigned long long xen_read_pmc(int counter)
{
- if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
+ if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
+ boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
return xen_amd_read_pmc(counter);
else
return xen_intel_read_pmc(counter);
--
2.7.4
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