On 02/03/2018 18:35, Stefano Stabellini wrote:
On Fri, 2 Mar 2018, Andrew Cooper wrote:
On 02/03/18 18:26, Stefano Stabellini wrote:
Suggested-by: Julien Grall
Signed-off-by: Stefano Stabellini
---
Changes in v3:
- new patch
---
Interestingly I couldn't find a better way in C89 to print
On Fri, 2 Mar 2018, Andrew Cooper wrote:
> On 02/03/18 18:26, Stefano Stabellini wrote:
> >
> >>> Suggested-by: Julien Grall
> >>> Signed-off-by: Stefano Stabellini
> >>>
> >>> ---
> >>> Changes in v3:
> >>> - new patch
> >>>
> >>> ---
> >>> Interestingly I couldn't find a better way in C89 to pr
On 02/03/18 18:26, Stefano Stabellini wrote:
>
>>> Suggested-by: Julien Grall
>>> Signed-off-by: Stefano Stabellini
>>>
>>> ---
>>> Changes in v3:
>>> - new patch
>>>
>>> ---
>>> Interestingly I couldn't find a better way in C89 to printk a size_t
>>> than casting it to unsigned long.
>> You can
On Fri, 2 Mar 2018, Julien Grall wrote:
> Hi Stefano,
>
> On 01/03/18 23:26, Stefano Stabellini wrote:
> > Even different cpus in big.LITTLE systems are expected to have the same
> > cacheline size. Unless the minimum of all cacheline sizes is used across
> > all cpu cores, cache coherency protoco
Hi Stefano,
On 01/03/18 23:26, Stefano Stabellini wrote:
Even different cpus in big.LITTLE systems are expected to have the same
cacheline size. Unless the minimum of all cacheline sizes is used across
all cpu cores, cache coherency protocols can go wrong. Instead, for
now, just disable any cpu
