On 12/02/18 18:23, Andre Przywara wrote:
Hi,
Hi Andre,
On 12/02/18 15:19, Julien Grall wrote:
Hi Andre,
On 09/02/18 14:39, Andre Przywara wrote:
The ARM Generic Timer uses a level-sensitive interrupt semantic. We
easily catch when the line goes high, as this triggers the hardware IRQ.
Ho
Hi,
On 12/02/18 15:19, Julien Grall wrote:
> Hi Andre,
>
> On 09/02/18 14:39, Andre Przywara wrote:
>> The ARM Generic Timer uses a level-sensitive interrupt semantic. We
>> easily catch when the line goes high, as this triggers the hardware IRQ.
>> However we have to sync the state of the interr
Hi Andre,
On 09/02/18 14:39, Andre Przywara wrote:
The ARM Generic Timer uses a level-sensitive interrupt semantic. We
easily catch when the line goes high, as this triggers the hardware IRQ.
However we have to sync the state of the interrupt condition at certain
points to catch when the line go
