RE: [Xen-ia64-devel] Where are DTR6 and DTRA defined and set?

Basically Isaku is correct, I suppose you are using Montecito, there are two threads per core. These two threads share TLB cache. There is a field tid in TLB entry to identify which thread this TLb entry belongs to. Usually TLB entry #0 belongs to thread 0 TLB entry #1 belongs to thread 1 TLB

[Xen-ia64-devel] Xen/IPF Unstable CS#17766 Status Report --- no new issue

Hi all, All the cases passed in this Cset. Detail Xen/IA64 Unstable Cset #17766 Status Report Test Result Summary: # total case: 17 # passed case: 17 # failed case: 0