# HG changeset patch
# User Jimi Xenidis <[EMAIL PROTECTED]>
# Node ID 9d85d34325b6052f1172e4d24cda3d323ffab62d
# Parent 9c485899125450b3901ecb664e71c26a75009c8e
[POWERPC][XEN] Make DAMN sure the HIDs and HIOR are correct for all processors
Signed-off-by: Jimi Xenidis <[EMAIL PROTECTED]>
---
xen/arch/powerpc/powerpc64/ppc970.c | 41 ++++++++++++++++++++------
xen/include/asm-powerpc/powerpc64/processor.h | 18 +++++++++++
xen/include/asm-powerpc/reg_defs.h | 1
3 files changed, 51 insertions(+), 9 deletions(-)
diff -r 9c4858991254 -r 9d85d34325b6 xen/arch/powerpc/powerpc64/ppc970.c
--- a/xen/arch/powerpc/powerpc64/ppc970.c Tue Aug 29 07:07:57 2006 -0400
+++ b/xen/arch/powerpc/powerpc64/ppc970.c Tue Aug 29 16:46:52 2006 -0400
@@ -90,11 +90,35 @@ unsigned int cpu_extent_order(void)
return log_large_page_sizes[0] - PAGE_SHIFT;
}
+static u64 cpu0_hids[6];
+static u64 cpu0_hior;
+
void cpu_initialize(int cpuid)
{
ulong r1, r2;
+ union hid0 hid0;
+ union hid1 hid1;
+ union hid4 hid4;
+ union hid5 hid5;
+
__asm__ __volatile__ ("mr %0, 1" : "=r" (r1));
__asm__ __volatile__ ("mr %0, 2" : "=r" (r2));
+
+ if (cpuid == 0) {
+ /* we can assume that these are sane to start with. We
+ * _do_not_ store the results in case we want to mess with them
+ * on a per-cpu basis later. */
+ cpu0_hids[0] = mfhid0();
+ cpu0_hids[1] = mfhid1();
+ cpu0_hids[4] = mfhid4();
+ cpu0_hids[5] = mfhid5();
+ cpu0_hior = 0;
+ }
+
+ hid0.word = cpu0_hids[0];
+ hid1.word = cpu0_hids[1];
+ hid4.word = cpu0_hids[4];
+ hid5.word = cpu0_hids[5];
/* This is SMP safe because the compiler must use r13 for it. */
parea = global_cpu_table[cpuid];
@@ -108,9 +132,6 @@ void cpu_initialize(int cpuid)
mtdec(timebase_freq);
mthdec(timebase_freq);
- union hid0 hid0;
-
- hid0.word = mfhid0();
hid0.bits.nap = 1;
hid0.bits.dpm = 1;
hid0.bits.nhr = 1;
@@ -134,9 +155,6 @@ void cpu_initialize(int cpuid)
mthid0(hid0.word);
- union hid1 hid1;
-
- hid1.word = mfhid1();
hid1.bits.bht_pm = 7;
hid1.bits.en_ls = 1;
@@ -153,13 +171,18 @@ void cpu_initialize(int cpuid)
hid1.bits.en_sp_itw = 1;
mthid1(hid1.word);
- union hid5 hid5;
-
- hid5.word = mfhid5();
+ /* no changes to hid4 but we want to make sure that secondaries
+ * are sane */
+ if (cpuid > 0)
+ mthid4(hid4.word);
+
hid5.bits.DCBZ_size = 0;
hid5.bits.DCBZ32_ill = 0;
mthid5(hid5.word);
+ mthior(cpu0_hior);
+
+ /* for good luck */
__asm__ __volatile__("isync; slbia; isync" : : : "memory");
}
diff -r 9c4858991254 -r 9d85d34325b6
xen/include/asm-powerpc/powerpc64/processor.h
--- a/xen/include/asm-powerpc/powerpc64/processor.h Tue Aug 29 07:07:57
2006 -0400
+++ b/xen/include/asm-powerpc/powerpc64/processor.h Tue Aug 29 16:46:52
2006 -0400
@@ -189,5 +189,23 @@ static inline void mthid5(ulong val)
: : "i"(SPRN_HID5), "r"(val));
}
+static inline void mthrmor(ulong val)
+{
+ __asm__ __volatile__ (
+ "sync\n"
+ "mtspr %0, %1\n"
+ "isync\n"
+ : : "i"(SPRN_HRMOR), "r"(val));
+}
+
+static inline void mthior(ulong val)
+{
+ __asm__ __volatile__ (
+ "sync\n"
+ "mtspr %0, %1\n"
+ "isync\n"
+ : : "i"(SPRN_HIOR), "r"(val));
+}
+
#endif /* __ASSEMBLY__ */
#endif
diff -r 9c4858991254 -r 9d85d34325b6 xen/include/asm-powerpc/reg_defs.h
--- a/xen/include/asm-powerpc/reg_defs.h Tue Aug 29 07:07:57 2006 -0400
+++ b/xen/include/asm-powerpc/reg_defs.h Tue Aug 29 16:46:52 2006 -0400
@@ -154,6 +154,7 @@
#define SPRN_HSPRG0 304
#define SPRN_HSPRG1 305
#define SPRN_HDEC 310
+#define SPRN_HIOR 311
#define SPRN_RMOR 312
#define SPRN_HRMOR 313
#define SPRN_HSRR0 314
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