# HG changeset patch
# User Jimi Xenidis <[EMAIL PROTECTED]>
# Node ID 3adb8d61d667d977e967c7e757ef0775ef4c283d
# Parent  bde996cddbbaea72c260b04fd6b95c5f43973f67
[ppc] Handle memory accesses based on the MSR value

While in real mode, the upper bits of an effective address is
truncated, RW does not take care of this automaically.  This allows us
to debug the real mode areas of the linux kernel, especially the early
boot phase.

Signed-off-by: Jimi Xenidis <[EMAIL PROTECTED]>
---
 tools/gpproxy/riscwatch.py |   31 +++++++++++++++++++++++++------
 1 files changed, 25 insertions(+), 6 deletions(-)

diff -r bde996cddbba -r 3adb8d61d667 tools/gpproxy/riscwatch.py
--- a/tools/gpproxy/riscwatch.py        Wed Jul 26 13:48:25 2006 -0400
+++ b/tools/gpproxy/riscwatch.py        Wed Jul 26 13:51:44 2006 -0400
@@ -76,6 +76,17 @@ class RISCWatchSession:
                self.telnet.write(cmd)
                return self._getprompt()
 
+       def adjust_addr(self, addr):
+               msr = int(self.get_register("msr"), 16)
+               # could come in as string or int
+               try:
+                       val = int(addr)
+               except:
+                       val = int(addr, 16)
+               if ((msr & 0x30) != 0x30) :
+                       val = val & ~(0xc000000000000000)
+               return val
+       
        def _command(self, cmd):
                """Send command and consume the echo."""
                cmd += "\n"
@@ -160,6 +171,7 @@ class RISCWatchSession:
 
        def set_memory(self, addr, len, val):
                assert len < 32
+               addr = self.adjust_addr(addr)
                result = self._command("m -d%d %x=%x" % (len, addr, val))
                m = ERRVAL.match(result)
                if m:
@@ -184,6 +196,7 @@ class RISCWatchSession:
                                if remaining >= size:
                                        break
 
+                       addr = self.adjust_addr(addr)
                        # do the read
                        hexaddr = "%x" % (addr + pos)
                        val = self._command("m -d%s %s" % (size, hexaddr))
@@ -206,36 +219,42 @@ class RISCWatchSession:
 
        def step(self, signal=None, addr=None):
                if addr:
-                       self._command("s 1 %s" % addr)
+                       addr = self.adjust_addr(addr)
+                       self._command("s 1 %x" % addr)
                else:
                        self._command("s")
 
        def resume(self, signal=None, addr=None):
                if addr:
-                       self._command("r %s" % addr)
+                       addr = self.adjust_addr(addr)
+                       self._command("r %x" % addr)
                else:
                        self._command("r")
 
        def break_insert_mem(self, addr):
-               result = self._command("bp %s" % addr)
+               addr = self.adjust_addr(addr)
+               result = self._command("bp %x" % addr)
                m = ERRVAL.match(result)
                if m:
                        raise IOError(m.group(2))
 
        def break_remove_mem(self, addr):
-               result = self._command("bp -r %s" % addr)
+               addr = self.adjust_addr(addr)
+               result = self._command("bp -r %x" % addr)
                m = ERRVAL.match(result)
                if m:
                        raise IOError(m.group(2))
 
        def break_insert_hardware(self, addr):
-               result = self._command("bp -h %s" % addr)
+               addr = self.adjust_addr(addr)
+               result = self._command("bp -h %x" % addr)
                m = ERRVAL.match(result)
                if m:
                        raise IOError(m.group(2))
 
        def break_remove_hardware(self, addr):
-               result = self._command("bp -h -r %s" % addr)
+               addr = self.adjust_addr(addr)
+               result = self._command("bp -h -r %x" % addr)
                m = ERRVAL.match(result)
                if m:
                        raise IOError(m.group(2))

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