On Sep 8, 2006, at 12:00 PM, Amos Waterland wrote:
The SMP timebase sync code that recently went in has a race in which
secondary processor X+1 can potentially take the timebase offset
that is
still in flight for secondary processor X. The cause of this was
marking a secondary processor online from the boot cpu and then trying
to wait for the secondary processor to mark itself online.
Signed-off-by: Amos Waterland <[EMAIL PROTECTED]>
Brain-fart-by: Jimi Xenidis <[EMAIL PROTECTED]>
Thanks amos
-JX
_______________________________________________
Xen-ppc-devel mailing list
Xen-ppc-devel@lists.xensource.com
http://lists.xensource.com/xen-ppc-devel