Hi all,
As I understand about adeos timer interrupt handling for the arch ARM integrator :
- the timer is acknowledged (clearing timer interrupt bit) if there is only one domain
- when many domains, timer interrupt bit is not cleared (I supposed to let other domains being aware of the timer interrupt)
Concerning the AT91RM9200 target, timer interrupt works in a slightly different way:
- the interrupt line is shared between all core peripherals (this include system timer but also memory controller, power management...)
- to detect if the IRQ comes really from the timer, I need to read the timer status register
The problem is that reading the timer status register automatically resets it, clearing any interrupt bit.
Whereas the timer interrupt bit is manually controlled in the integrator architecture, it seems that I can't do the same on the AT91RM9200 architecture.
Can anybody confirm my understanding of the adeos timer interrupt handling ?
If I'm right, then is there any other way to deal with the timer interrupt for the AT91RM9200 ?
Last question, where can I find documentation about adeos internal (description of functions, global variables, IRQ handling and so on) ?
Best regards
Yann Leprovost
_______________________________________________ Xenomai-core mailing list Xenomai-core@gna.org https://mail.gna.org/listinfo/xenomai-core
