On Mon, Feb 11, 2008 at 2:41 PM, Jan Kiszka [EMAIL PROTECTED] wrote:
Gilles Chanteperdrix wrote:
Juan Antonio Garcia Redondo wrote:
On 23/01/08 14:15, Gilles Chanteperdrix wrote:
On Jan 23, 2008 11:04 AM, Gilles Chanteperdrix
[EMAIL PROTECTED] wrote:
On Jan 23, 2008
Jan Kiszka wrote:
There is a shadow relax procedure running before the timer IRQ fires,
and that takes another context switch. So the latency sum is:
- unrelated context switch
- timer IRQ
- switch to woken up RT process
- serial IRQ
Almost the theoretical worst case.
The
Gilles Chanteperdrix wrote:
On Mon, Feb 11, 2008 at 2:41 PM, Jan Kiszka [EMAIL PROTECTED] wrote:
Gilles Chanteperdrix wrote:
Juan Antonio Garcia Redondo wrote:
On 23/01/08 14:15, Gilles Chanteperdrix wrote:
On Jan 23, 2008 11:04 AM, Gilles Chanteperdrix
[EMAIL PROTECTED]
Gilles Chanteperdrix wrote:
And another here, whereas if I understand correctly, the mm did not
change. So, this is probably an unwanted effect of the cache flush
optimization in the arm patch.
I will now try to understand if this second cache flush is really normal.
Yes, it is
Gilles Chanteperdrix wrote:
Juan Antonio Garcia Redondo wrote:
On 23/01/08 14:15, Gilles Chanteperdrix wrote:
On Jan 23, 2008 11:04 AM, Gilles Chanteperdrix
[EMAIL PROTECTED] wrote:
On Jan 23, 2008 7:52 AM, Juan Antonio Garcia Redondo
[EMAIL PROTECTED] wrote:
I see
