[Xenomai-git] Gilles Chanteperdrix : blackfin: adapt to refactored timers
Module: xenomai-forge Branch: master Commit: 5e090f757621d3e9c8fe62c2c91ead1a6ec94e28 URL: http://git.xenomai.org/?p=xenomai-forge.git;a=commit;h=5e090f757621d3e9c8fe62c2c91ead1a6ec94e28 Author: Gilles Chanteperdrix gilles.chanteperd...@xenomai.org Date: Sun Apr 15 23:25:25 2012 +0200 blackfin: adapt to refactored timers --- include/asm-blackfin/hal.h| 12 +++ kernel/cobalt/arch/blackfin/hal.c | 38 ++-- 2 files changed, 43 insertions(+), 7 deletions(-) diff --git a/include/asm-blackfin/hal.h b/include/asm-blackfin/hal.h index 1887497..35c7f01 100644 --- a/include/asm-blackfin/hal.h +++ b/include/asm-blackfin/hal.h @@ -30,7 +30,11 @@ #include asm/div64.h #define RTHAL_ARCH_NAMEblackfin +#ifndef CONFIG_IPIPE_CORE #define RTHAL_TIMER_DEVICE coretmr +#else /* CONFIG_IPIPE_CORE */ +#define RTHAL_TIMER_DEVICE (ipipe_timer_name()) +#endif /* CONFIG_IPIPE_CORE */ #define RTHAL_CLOCK_DEVICE cyclectr typedef unsigned long long rthal_time_t; @@ -47,7 +51,11 @@ static inline __attribute_const__ unsigned long ffnz(unsigned long ul) #include asm/processor.h #include asm/xenomai/atomic.h +#ifndef CONFIG_IPIPE_CORE #define RTHAL_TIMER_IRQIRQ_CORETMR +#else /* CONFIG_IPIPE_CORE */ +#define RTHAL_TIMER_IRQ__ipipe_hrtimer_irq +#endif /* CONFIG_IPIPE_CORE */ #define RTHAL_HOST_TICK_IRQRTHAL_TIMER_IRQ /* The NMI watchdog timer is clocked by the system clock. */ @@ -65,6 +73,7 @@ static inline unsigned long long rthal_rdtsc(void) static inline void rthal_timer_program_shot(unsigned long delay) { +#ifndef CONFIG_IPIPE_CORE if (delay 2) ipipe_post_irq_head(RTHAL_TIMER_IRQ); else { @@ -74,6 +83,9 @@ static inline void rthal_timer_program_shot(unsigned long delay) CSYNC(); bfin_write_TCNTL(TMPWR | TMREN); } +#else /* !CONFIG_IPIPE_CORE */ + ipipe_timer_set(delay); +#endif /* !CONFIG_IPIPE_CORE */ } /* Private interface -- Internal use only */ diff --git a/kernel/cobalt/arch/blackfin/hal.c b/kernel/cobalt/arch/blackfin/hal.c index 808eb2d..57b4ae1 100644 --- a/kernel/cobalt/arch/blackfin/hal.c +++ b/kernel/cobalt/arch/blackfin/hal.c @@ -40,6 +40,8 @@ enum rthal_ktimer_mode rthal_ktimer_saved_mode; +#ifndef CONFIG_IPIPE_CORE + #define RTHAL_SET_ONESHOT_XENOMAI 1 #define RTHAL_SET_ONESHOT_LINUX2 #define RTHAL_SET_PERIODIC 3 @@ -93,6 +95,12 @@ static void rthal_timer_set_periodic(void) rthal_setup_periodic_coretmr(); ipipe_critical_exit(flags); } +#else /* I-pipe core */ +#define rthal_setup_oneshot_coretmr() do { } while (0) +#define rthal_setup_periodic_coretmr() do { } while (0) +#define rthal_timer_set_oneshot(rt_mode) do { } while (0) +#define rthal_timer_set_periodic() do { } while (0) +#endif /* I-pipe core */ static int cpu_timers_requested; @@ -106,11 +114,12 @@ int rthal_timer_request(void (*tick_handler)(void), unsigned long dummy, *tmfreq = dummy; int tickval, ret, res; - if (rthal_timerfreq_arg == 0) - tmfreq = rthal_archdata.timer_freq; - +#ifndef CONFIG_IPIPE_CORE res = ipipe_request_tickdev(bfin_core_timer, mode_emul, tick_emul, cpu, tmfreq); +#else /* I-pipe timers */ + res = ipipe_timer_start(tick_handler, mode_emul, tick_emul, cpu); +#endif /* I-pipe timers */ switch (res) { case CLOCK_EVT_MODE_PERIODIC: /* Oneshot tick emulation callback won't be used, ask @@ -151,12 +160,14 @@ int rthal_timer_request(void (*tick_handler)(void), if (cpu_timers_requested++ 0) goto out; +#ifndef CONFIG_IPIPE_CORE ret = ipipe_request_irq(rthal_archdata.domain, RTHAL_TIMER_IRQ, (ipipe_irq_handler_t)tick_handler, NULL, NULL); if (ret) return ret; +#endif /* !I-pipe core */ rthal_timer_set_oneshot(1); @@ -166,12 +177,18 @@ out: void rthal_timer_release(int cpu) { +#ifndef CONFIG_IPIPE_CORE ipipe_release_tickdev(cpu); +#else /* I-pipe core */ + ipipe_timer_stop(cpu); +#endif /* I-pipe core */ if (--cpu_timers_requested 0) return; +#ifndef CONFIG_IPIPE_CORE ipipe_free_irq(rthal_archdata.domain, RTHAL_TIMER_IRQ); +#endif /* !I-pipe core */ if (rthal_ktimer_saved_mode == KTIMER_MODE_PERIODIC) rthal_timer_set_periodic(); @@ -203,21 +220,28 @@ void xnpod_schedule_deferred(void); int rthal_arch_init(void) { +#ifdef CONFIG_IPIPE_CORE + int rc = ipipe_timers_request(); + if (rc 0) + return rc; +#endif /* CONFIG_IPIPE_CORE */ + __ipipe_irq_tail_hook = (unsigned long)xnpod_schedule_deferred; if (rthal_clockfreq_arg == 0)
[Xenomai-git] Gilles Chanteperdrix : blackfin: adapt to refactored timers
Module: xenomai-gch Branch: for-forge Commit: ca4599f6ac4ccd6cfbc62b1e2d6eba9d28f3 URL: http://git.xenomai.org/?p=xenomai-gch.git;a=commit;h=ca4599f6ac4ccd6cfbc62b1e2d6eba9d28f3 Author: Gilles Chanteperdrix gilles.chanteperd...@xenomai.org Date: Sun Apr 15 23:25:25 2012 +0200 blackfin: adapt to refactored timers --- include/asm-blackfin/bits/timer.h |4 include/asm-blackfin/hal.h| 12 kernel/cobalt/arch/blackfin/hal.c | 29 + 3 files changed, 45 insertions(+), 0 deletions(-) diff --git a/include/asm-blackfin/bits/timer.h b/include/asm-blackfin/bits/timer.h index 9c0f685..ca79b00 100644 --- a/include/asm-blackfin/bits/timer.h +++ b/include/asm-blackfin/bits/timer.h @@ -26,9 +26,13 @@ static inline void xnarch_program_timer_shot(unsigned long delay) { +#ifndef CONFIG_IPIPE_CORE /* The core timer runs at the core clock rate -- therefore no conversion is needed between TSC and delay values. */ rthal_timer_program_shot(delay); +#else /* !CONFIG_IPIPE_CORE */ + ipipe_timer_set(delay); +#endif /* !CONFIG_IPIPE_CORE */ } static inline void xnarch_send_timer_ipi(xnarch_cpumask_t mask) diff --git a/include/asm-blackfin/hal.h b/include/asm-blackfin/hal.h index 1887497..35c7f01 100644 --- a/include/asm-blackfin/hal.h +++ b/include/asm-blackfin/hal.h @@ -30,7 +30,11 @@ #include asm/div64.h #define RTHAL_ARCH_NAMEblackfin +#ifndef CONFIG_IPIPE_CORE #define RTHAL_TIMER_DEVICE coretmr +#else /* CONFIG_IPIPE_CORE */ +#define RTHAL_TIMER_DEVICE (ipipe_timer_name()) +#endif /* CONFIG_IPIPE_CORE */ #define RTHAL_CLOCK_DEVICE cyclectr typedef unsigned long long rthal_time_t; @@ -47,7 +51,11 @@ static inline __attribute_const__ unsigned long ffnz(unsigned long ul) #include asm/processor.h #include asm/xenomai/atomic.h +#ifndef CONFIG_IPIPE_CORE #define RTHAL_TIMER_IRQIRQ_CORETMR +#else /* CONFIG_IPIPE_CORE */ +#define RTHAL_TIMER_IRQ__ipipe_hrtimer_irq +#endif /* CONFIG_IPIPE_CORE */ #define RTHAL_HOST_TICK_IRQRTHAL_TIMER_IRQ /* The NMI watchdog timer is clocked by the system clock. */ @@ -65,6 +73,7 @@ static inline unsigned long long rthal_rdtsc(void) static inline void rthal_timer_program_shot(unsigned long delay) { +#ifndef CONFIG_IPIPE_CORE if (delay 2) ipipe_post_irq_head(RTHAL_TIMER_IRQ); else { @@ -74,6 +83,9 @@ static inline void rthal_timer_program_shot(unsigned long delay) CSYNC(); bfin_write_TCNTL(TMPWR | TMREN); } +#else /* !CONFIG_IPIPE_CORE */ + ipipe_timer_set(delay); +#endif /* !CONFIG_IPIPE_CORE */ } /* Private interface -- Internal use only */ diff --git a/kernel/cobalt/arch/blackfin/hal.c b/kernel/cobalt/arch/blackfin/hal.c index 808eb2d..8730095 100644 --- a/kernel/cobalt/arch/blackfin/hal.c +++ b/kernel/cobalt/arch/blackfin/hal.c @@ -40,6 +40,8 @@ enum rthal_ktimer_mode rthal_ktimer_saved_mode; +#ifndef CONFIG_IPIPE_CORE + #define RTHAL_SET_ONESHOT_XENOMAI 1 #define RTHAL_SET_ONESHOT_LINUX2 #define RTHAL_SET_PERIODIC 3 @@ -93,6 +95,12 @@ static void rthal_timer_set_periodic(void) rthal_setup_periodic_coretmr(); ipipe_critical_exit(flags); } +#else /* I-pipe core */ +#define rthal_setup_oneshot_coretmr() do { } while (0) +#define rthal_setup_periodic_coretmr() do { } while (0) +#define rthal_timer_set_oneshot(rt_mode) do { } while (0) +#define rthal_timer_set_periodic() do { } while (0) +#endif /* I-pipe core */ static int cpu_timers_requested; @@ -109,8 +117,12 @@ int rthal_timer_request(void (*tick_handler)(void), if (rthal_timerfreq_arg == 0) tmfreq = rthal_archdata.timer_freq; +#ifndef CONFIG_IPIPE_CORE res = ipipe_request_tickdev(bfin_core_timer, mode_emul, tick_emul, cpu, tmfreq); +#else /* I-pipe timers */ + res = ipipe_timer_start(tick_handler, mode_emul, tick_emul, cpu); +#endif /* I-pipe timers */ switch (res) { case CLOCK_EVT_MODE_PERIODIC: /* Oneshot tick emulation callback won't be used, ask @@ -151,12 +163,14 @@ int rthal_timer_request(void (*tick_handler)(void), if (cpu_timers_requested++ 0) goto out; +#ifndef CONFIG_IPIPE_CORE ret = ipipe_request_irq(rthal_archdata.domain, RTHAL_TIMER_IRQ, (ipipe_irq_handler_t)tick_handler, NULL, NULL); if (ret) return ret; +#endif /* !I-pipe core */ rthal_timer_set_oneshot(1); @@ -166,12 +180,18 @@ out: void rthal_timer_release(int cpu) { +#ifndef CONFIG_IPIPE_CORE ipipe_release_tickdev(cpu); +#else /* I-pipe core */ + ipipe_timer_stop(cpu); +#endif /* I-pipe core */ if (--cpu_timers_requested 0)
[Xenomai-git] Gilles Chanteperdrix : blackfin: adapt to refactored timers
Module: xenomai-gch Branch: for-forge Commit: 891f1dfd73d792b80b9e36b1048885e12c5bccfa URL: http://git.xenomai.org/?p=xenomai-gch.git;a=commit;h=891f1dfd73d792b80b9e36b1048885e12c5bccfa Author: Gilles Chanteperdrix gilles.chanteperd...@xenomai.org Date: Sun Apr 15 23:25:25 2012 +0200 blackfin: adapt to refactored timers --- include/asm-blackfin/hal.h| 12 kernel/cobalt/arch/blackfin/hal.c | 29 + 2 files changed, 41 insertions(+), 0 deletions(-) diff --git a/include/asm-blackfin/hal.h b/include/asm-blackfin/hal.h index 1887497..35c7f01 100644 --- a/include/asm-blackfin/hal.h +++ b/include/asm-blackfin/hal.h @@ -30,7 +30,11 @@ #include asm/div64.h #define RTHAL_ARCH_NAMEblackfin +#ifndef CONFIG_IPIPE_CORE #define RTHAL_TIMER_DEVICE coretmr +#else /* CONFIG_IPIPE_CORE */ +#define RTHAL_TIMER_DEVICE (ipipe_timer_name()) +#endif /* CONFIG_IPIPE_CORE */ #define RTHAL_CLOCK_DEVICE cyclectr typedef unsigned long long rthal_time_t; @@ -47,7 +51,11 @@ static inline __attribute_const__ unsigned long ffnz(unsigned long ul) #include asm/processor.h #include asm/xenomai/atomic.h +#ifndef CONFIG_IPIPE_CORE #define RTHAL_TIMER_IRQIRQ_CORETMR +#else /* CONFIG_IPIPE_CORE */ +#define RTHAL_TIMER_IRQ__ipipe_hrtimer_irq +#endif /* CONFIG_IPIPE_CORE */ #define RTHAL_HOST_TICK_IRQRTHAL_TIMER_IRQ /* The NMI watchdog timer is clocked by the system clock. */ @@ -65,6 +73,7 @@ static inline unsigned long long rthal_rdtsc(void) static inline void rthal_timer_program_shot(unsigned long delay) { +#ifndef CONFIG_IPIPE_CORE if (delay 2) ipipe_post_irq_head(RTHAL_TIMER_IRQ); else { @@ -74,6 +83,9 @@ static inline void rthal_timer_program_shot(unsigned long delay) CSYNC(); bfin_write_TCNTL(TMPWR | TMREN); } +#else /* !CONFIG_IPIPE_CORE */ + ipipe_timer_set(delay); +#endif /* !CONFIG_IPIPE_CORE */ } /* Private interface -- Internal use only */ diff --git a/kernel/cobalt/arch/blackfin/hal.c b/kernel/cobalt/arch/blackfin/hal.c index 808eb2d..8730095 100644 --- a/kernel/cobalt/arch/blackfin/hal.c +++ b/kernel/cobalt/arch/blackfin/hal.c @@ -40,6 +40,8 @@ enum rthal_ktimer_mode rthal_ktimer_saved_mode; +#ifndef CONFIG_IPIPE_CORE + #define RTHAL_SET_ONESHOT_XENOMAI 1 #define RTHAL_SET_ONESHOT_LINUX2 #define RTHAL_SET_PERIODIC 3 @@ -93,6 +95,12 @@ static void rthal_timer_set_periodic(void) rthal_setup_periodic_coretmr(); ipipe_critical_exit(flags); } +#else /* I-pipe core */ +#define rthal_setup_oneshot_coretmr() do { } while (0) +#define rthal_setup_periodic_coretmr() do { } while (0) +#define rthal_timer_set_oneshot(rt_mode) do { } while (0) +#define rthal_timer_set_periodic() do { } while (0) +#endif /* I-pipe core */ static int cpu_timers_requested; @@ -109,8 +117,12 @@ int rthal_timer_request(void (*tick_handler)(void), if (rthal_timerfreq_arg == 0) tmfreq = rthal_archdata.timer_freq; +#ifndef CONFIG_IPIPE_CORE res = ipipe_request_tickdev(bfin_core_timer, mode_emul, tick_emul, cpu, tmfreq); +#else /* I-pipe timers */ + res = ipipe_timer_start(tick_handler, mode_emul, tick_emul, cpu); +#endif /* I-pipe timers */ switch (res) { case CLOCK_EVT_MODE_PERIODIC: /* Oneshot tick emulation callback won't be used, ask @@ -151,12 +163,14 @@ int rthal_timer_request(void (*tick_handler)(void), if (cpu_timers_requested++ 0) goto out; +#ifndef CONFIG_IPIPE_CORE ret = ipipe_request_irq(rthal_archdata.domain, RTHAL_TIMER_IRQ, (ipipe_irq_handler_t)tick_handler, NULL, NULL); if (ret) return ret; +#endif /* !I-pipe core */ rthal_timer_set_oneshot(1); @@ -166,12 +180,18 @@ out: void rthal_timer_release(int cpu) { +#ifndef CONFIG_IPIPE_CORE ipipe_release_tickdev(cpu); +#else /* I-pipe core */ + ipipe_timer_stop(cpu); +#endif /* I-pipe core */ if (--cpu_timers_requested 0) return; +#ifndef CONFIG_IPIPE_CORE ipipe_free_irq(rthal_archdata.domain, RTHAL_TIMER_IRQ); +#endif /* !I-pipe core */ if (rthal_ktimer_saved_mode == KTIMER_MODE_PERIODIC) rthal_timer_set_periodic(); @@ -203,6 +223,12 @@ void xnpod_schedule_deferred(void); int rthal_arch_init(void) { +#ifdef CONFIG_IPIPE_CORE + int rc = ipipe_timers_request(); + if (rc 0) + return rc; +#endif /* CONFIG_IPIPE_CORE */ + __ipipe_irq_tail_hook = (unsigned long)xnpod_schedule_deferred; if (rthal_clockfreq_arg == 0) @@ -218,6 +244,9 @@ int rthal_arch_init(void) void rthal_arch_cleanup(void) { +#ifdef CONFIG_IPIPE_CORE
[Xenomai-git] Gilles Chanteperdrix : blackfin: adapt to refactored timers
Module: xenomai-gch Branch: for-forge Commit: 5e090f757621d3e9c8fe62c2c91ead1a6ec94e28 URL: http://git.xenomai.org/?p=xenomai-gch.git;a=commit;h=5e090f757621d3e9c8fe62c2c91ead1a6ec94e28 Author: Gilles Chanteperdrix gilles.chanteperd...@xenomai.org Date: Sun Apr 15 23:25:25 2012 +0200 blackfin: adapt to refactored timers --- include/asm-blackfin/hal.h| 12 +++ kernel/cobalt/arch/blackfin/hal.c | 38 ++-- 2 files changed, 43 insertions(+), 7 deletions(-) diff --git a/include/asm-blackfin/hal.h b/include/asm-blackfin/hal.h index 1887497..35c7f01 100644 --- a/include/asm-blackfin/hal.h +++ b/include/asm-blackfin/hal.h @@ -30,7 +30,11 @@ #include asm/div64.h #define RTHAL_ARCH_NAMEblackfin +#ifndef CONFIG_IPIPE_CORE #define RTHAL_TIMER_DEVICE coretmr +#else /* CONFIG_IPIPE_CORE */ +#define RTHAL_TIMER_DEVICE (ipipe_timer_name()) +#endif /* CONFIG_IPIPE_CORE */ #define RTHAL_CLOCK_DEVICE cyclectr typedef unsigned long long rthal_time_t; @@ -47,7 +51,11 @@ static inline __attribute_const__ unsigned long ffnz(unsigned long ul) #include asm/processor.h #include asm/xenomai/atomic.h +#ifndef CONFIG_IPIPE_CORE #define RTHAL_TIMER_IRQIRQ_CORETMR +#else /* CONFIG_IPIPE_CORE */ +#define RTHAL_TIMER_IRQ__ipipe_hrtimer_irq +#endif /* CONFIG_IPIPE_CORE */ #define RTHAL_HOST_TICK_IRQRTHAL_TIMER_IRQ /* The NMI watchdog timer is clocked by the system clock. */ @@ -65,6 +73,7 @@ static inline unsigned long long rthal_rdtsc(void) static inline void rthal_timer_program_shot(unsigned long delay) { +#ifndef CONFIG_IPIPE_CORE if (delay 2) ipipe_post_irq_head(RTHAL_TIMER_IRQ); else { @@ -74,6 +83,9 @@ static inline void rthal_timer_program_shot(unsigned long delay) CSYNC(); bfin_write_TCNTL(TMPWR | TMREN); } +#else /* !CONFIG_IPIPE_CORE */ + ipipe_timer_set(delay); +#endif /* !CONFIG_IPIPE_CORE */ } /* Private interface -- Internal use only */ diff --git a/kernel/cobalt/arch/blackfin/hal.c b/kernel/cobalt/arch/blackfin/hal.c index 808eb2d..57b4ae1 100644 --- a/kernel/cobalt/arch/blackfin/hal.c +++ b/kernel/cobalt/arch/blackfin/hal.c @@ -40,6 +40,8 @@ enum rthal_ktimer_mode rthal_ktimer_saved_mode; +#ifndef CONFIG_IPIPE_CORE + #define RTHAL_SET_ONESHOT_XENOMAI 1 #define RTHAL_SET_ONESHOT_LINUX2 #define RTHAL_SET_PERIODIC 3 @@ -93,6 +95,12 @@ static void rthal_timer_set_periodic(void) rthal_setup_periodic_coretmr(); ipipe_critical_exit(flags); } +#else /* I-pipe core */ +#define rthal_setup_oneshot_coretmr() do { } while (0) +#define rthal_setup_periodic_coretmr() do { } while (0) +#define rthal_timer_set_oneshot(rt_mode) do { } while (0) +#define rthal_timer_set_periodic() do { } while (0) +#endif /* I-pipe core */ static int cpu_timers_requested; @@ -106,11 +114,12 @@ int rthal_timer_request(void (*tick_handler)(void), unsigned long dummy, *tmfreq = dummy; int tickval, ret, res; - if (rthal_timerfreq_arg == 0) - tmfreq = rthal_archdata.timer_freq; - +#ifndef CONFIG_IPIPE_CORE res = ipipe_request_tickdev(bfin_core_timer, mode_emul, tick_emul, cpu, tmfreq); +#else /* I-pipe timers */ + res = ipipe_timer_start(tick_handler, mode_emul, tick_emul, cpu); +#endif /* I-pipe timers */ switch (res) { case CLOCK_EVT_MODE_PERIODIC: /* Oneshot tick emulation callback won't be used, ask @@ -151,12 +160,14 @@ int rthal_timer_request(void (*tick_handler)(void), if (cpu_timers_requested++ 0) goto out; +#ifndef CONFIG_IPIPE_CORE ret = ipipe_request_irq(rthal_archdata.domain, RTHAL_TIMER_IRQ, (ipipe_irq_handler_t)tick_handler, NULL, NULL); if (ret) return ret; +#endif /* !I-pipe core */ rthal_timer_set_oneshot(1); @@ -166,12 +177,18 @@ out: void rthal_timer_release(int cpu) { +#ifndef CONFIG_IPIPE_CORE ipipe_release_tickdev(cpu); +#else /* I-pipe core */ + ipipe_timer_stop(cpu); +#endif /* I-pipe core */ if (--cpu_timers_requested 0) return; +#ifndef CONFIG_IPIPE_CORE ipipe_free_irq(rthal_archdata.domain, RTHAL_TIMER_IRQ); +#endif /* !I-pipe core */ if (rthal_ktimer_saved_mode == KTIMER_MODE_PERIODIC) rthal_timer_set_periodic(); @@ -203,21 +220,28 @@ void xnpod_schedule_deferred(void); int rthal_arch_init(void) { +#ifdef CONFIG_IPIPE_CORE + int rc = ipipe_timers_request(); + if (rc 0) + return rc; +#endif /* CONFIG_IPIPE_CORE */ + __ipipe_irq_tail_hook = (unsigned long)xnpod_schedule_deferred; if (rthal_clockfreq_arg == 0)