On Thu, Sep 11, 2014 at 12:53:30PM -0700, Keith Packard wrote:
Chris Wilson ch...@chris-wilson.co.uk writes:
That extra alignment is due to gen2 and early gen3 (if
(!intel-has_relaxed_fencing) covers them).
Here's the patch which changed the alignment requirment:
[snip commits picked at
Chris Wilson ch...@chris-wilson.co.uk writes:
commit d21d781466785c317131a8a57606925867265dc8
Author: Daniel Vetter daniel.vet...@ffwll.ch
Date: Tue Feb 22 18:31:44 2011 +0100
Fix relaxed tiling on gen2
This one matches libdrm in using 16 for the tile height alignment on
gen2.
Try
On Wednesday, September 10, 2014 02:09:07 PM Keith Packard wrote:
Here are a couple of small bug fixes which make DRI3/Present work
better with UXA.
[PATCH 1/2] Do not clear pending kernel events on mode switch
This patch prevents GL-based compositing managers from wedging when
On Wed, Sep 10, 2014 at 02:09:07PM -0700, Keith Packard wrote:
[PATCH 2/2] Correct BO allocation alignment
This patch makes UXA and Mesa agree about how buffers are allocated
for images. Without this, UXA was requiring larger padding, which
meant that converting some textures into pixmaps
Why doesn't mesa allocate buffers in the same way for those chips, then?
Do you have any documentation about this?
On Thu, Sep 11, 2014 at 12:37 AM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Wed, Sep 10, 2014 at 02:09:07PM -0700, Keith Packard wrote:
[PATCH 2/2] Correct BO allocation
On Thu, Sep 11, 2014 at 12:47:21AM -0600, Jasper St. Pierre wrote:
Why doesn't mesa allocate buffers in the same way for those chips, then?
Good question.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
___
xorg-devel@lists.x.org:
Chris Wilson ch...@chris-wilson.co.uk writes:
That extra alignment is due to gen2 and early gen3 (if
(!intel-has_relaxed_fencing) covers them).
Here's the patch which changed the alignment requirment:
commit 736b89504a32239a0c7dfb5961c1b8292dd744bd
Author: Chris Wilson
