The PCI bridge resources are stored in pci_host_bridge.windows,
mem_base under pcie_port has been removed, so update the resources
interface to correctly identify pcie device
Signed-off-by: Xiaolei Wang
---
drivers/pci/controller/dwc/pci-imx6.c | 9 ++---
1 file changed, 6 insertions(+), 3
On Sun, Mar 21, 2021 at 9:57 PM Khem Raj wrote:
>
> On Sun, Mar 21, 2021 at 6:43 PM Bruce Ashfield
> wrote:
> >
> > On Sun, Mar 21, 2021 at 9:42 PM Khem Raj wrote:
> > >
> > > All warnings seems to fixed !! its on to do_compile now, so all seem to
> > > work
> > >
> >
> > Mine seemed to work
On Sun, Mar 21, 2021 at 6:43 PM Bruce Ashfield wrote:
>
> On Sun, Mar 21, 2021 at 9:42 PM Khem Raj wrote:
> >
> > All warnings seems to fixed !! its on to do_compile now, so all seem to work
> >
>
> Mine seemed to work as well, so I sent the SRCREV bump to OE core just
> now. There's no
> need
On Sun, Mar 21, 2021 at 9:42 PM Khem Raj wrote:
>
> All warnings seems to fixed !! its on to do_compile now, so all seem to work
>
Mine seemed to work as well, so I sent the SRCREV bump to OE core just
now. There's no
need to wait on it, since we know it is definitely better :D
If there are
All warnings seems to fixed !! its on to do_compile now, so all seem to work
On Sun, Mar 21, 2021 at 6:39 PM Khem Raj wrote:
>
> you changes are more complete then mine, thanks for taking care of
> this. I am testing latest tip now
>
> diff --git a/meta/recipes-kernel/linux/linux-yocto_5.10.bb
you changes are more complete then mine, thanks for taking care of
this. I am testing latest tip now
diff --git a/meta/recipes-kernel/linux/linux-yocto_5.10.bb
b/meta/recipes-kernel/linux/linux-yocto_5.10.bb
index 9c122832f4..ae4eea0096 100644
--- a/meta/recipes-kernel/linux/linux-yocto_5.10.bb
oh cool thanks :)
On Sun, Mar 21, 2021 at 6:34 PM Bruce Ashfield wrote:
>
> Heh.
>
> If you check the kernel-cache, I just made the same changes (with one
> additional):
>
> https://git.yoctoproject.org/cgit/cgit.cgi/yocto-kernel-cache/commit/?id=3f21857300e44105375dafefaa0a6c4be657560c
>
> So
Heh.
If you check the kernel-cache, I just made the same changes (with one
additional):
https://git.yoctoproject.org/cgit/cgit.cgi/yocto-kernel-cache/commit/?id=3f21857300e44105375dafefaa0a6c4be657560c
So we are in sync!
Bruce
On Sun, Mar 21, 2021 at 9:31 PM Khem Raj wrote:
>
> These options
These options end up with 'n' in qemuppc64 anyway
Signed-off-by: Khem Raj
Cc: Bruce Ashfield
---
bsp/qemu-ppc64/qemu-ppc64.cfg | 2 --
1 file changed, 2 deletions(-)
diff --git a/bsp/qemu-ppc64/qemu-ppc64.cfg b/bsp/qemu-ppc64/qemu-ppc64.cfg
index 68912490..402b04ec 100644
---
Applied.
The tools are also picking up some other warnings in my local testing
(with fixes that aren't yet sent for merging).
You saw this due to a bug in my proposed patch, but the issue is valid
(along with the other ones I found).
I've fixed them all and will send them in my next pull
Default qemuppc64 is LE now a days
Signed-off-by: Khem Raj
Cc: Bruce Ashfield
---
bsp/qemu-ppc64/qemu-ppc64.cfg | 1 -
1 file changed, 1 deletion(-)
diff --git a/bsp/qemu-ppc64/qemu-ppc64.cfg b/bsp/qemu-ppc64/qemu-ppc64.cfg
index f48a0136..68912490 100644
--- a/bsp/qemu-ppc64/qemu-ppc64.cfg
This is disabled in final defconfig anyway
Signed-off-by: Khem Raj
Cc: Bruce Ashfield
---
bsp/qemu-ppc64/qemu-ppc64.cfg | 1 -
1 file changed, 1 deletion(-)
diff --git a/bsp/qemu-ppc64/qemu-ppc64.cfg b/bsp/qemu-ppc64/qemu-ppc64.cfg
index 2bf1684d..f48a0136 100644
---
This is disabled in final defconfig anyway
Signed-off-by: Khem Raj
Cc: Bruce Ashfield
---
bsp/qemu-ppc64/qemu-ppc64.cfg | 1 -
1 file changed, 1 deletion(-)
diff --git a/bsp/qemu-ppc64/qemu-ppc64.cfg b/bsp/qemu-ppc64/qemu-ppc64.cfg
index 2bf1684d..f48a0136 100644
---
> // interrupt-parent = <>;
> // interrupts = <0 24 IRQ_TYPE_EDGE_FALLING>;
Not sure if you did represent these values correctly?!
I have for enc28j60:something like this:
interrupt-parent = <>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
Where <> is gpio chip name (the gpio port 2),
and <1
My problem is I have an 1553 chip (an avionic data bus) connected to the
HPS master (an ARM processor) via an FPGA (soft) SPI controller. This is
where the spi-altera.c comes in. It provides the driver/interface to the
soft SPI controller on the Arria 10 SoC.
I need an interface now to
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