From: Ng, Wei Tee wei.tee...@intel.com
Hi all,
This patch is to update valleyisland-io-pci.scc file to
merge new version of feature branch (valleyisland-io-4.0).
valleyisland-io-4.0 is the feature branch for Valley Island
BSP which was recently being rebase from version 1 to version 4.
This
From: Ng, Wei Tee wei.tee...@intel.com
valleyisland-io-4.0 is the feature branch for Valley Island BSP.
This feature branch was recently being rebased from version 1 to
version 4 (current version).This patch is to update Valley Island
scc file in order to merge version 4 feature branch.
From: Ng, Wei Tee wei.tee...@intel.com
Hi all,
This patch is to backport Baytrail bug fixes patches that are
available in the upstream kernel into Yocto Project linux
kernel v3.10. These bug fixes patches are related to I/O
driver such as GPIO, USB and DMA.
This configuration was buit and
From: Ng Wei Tee wei.tee...@intel.com
Hi all,
This patch is to add codec ID for Valleyview2 display codec which
can enable HDMI audio support. This patch is backported from upstream
kernel into Yocto Project linux kernel v3.10.
It was built with Valley Island configuration and tested working
on
From: Mengdong Lin mengdong@intel.com
This patch adds codec ID (0x80862882) and module alias for
Valleyview2 display codec.
Signed-off-by: Mengdong Lin mengdong@intel.com
Signed-off-by: Takashi Iwai ti...@suse.de
(cherry picked from commit cc1a95d9f6423ced191b6f264e9657d98844ea0d)
From: Ng Wei Tee wei.tee...@intel.com
This patch will enabled Wifi and Bluetooth driver by
using configs available in mwifiex.cfg, mac80211.cfg,
bluetooth.cfg and bluetooth-usb.cfg
Signed-off-by: Ng Wei Tee wei.tee...@intel.com
---
.../bsp/valleyisland/valleyisland-32.scc |7
From: Max Eliaser max.elia...@intel.com
Instead of adding CONFIG_BT directly to configuration fragments for various
BSPs, it's better to put it in its own fragment which can then be included
elsewhere.
This commit also adds the new features/bluetooth/bluetooth.scc to
intel-common-standard.scc,
From: Cristian Iorga cristian.io...@intel.com
Add support for USB-based generic Bluetooth hardware modules.
Partial fix for [YOCTO #6960].
Signed-off-by: Cristian Iorga cristian.io...@intel.com
Signed-off-by: Bruce Ashfield bruce.ashfi...@windriver.com
(cherry picked from commit
From: Cristian Iorga cristian.io...@intel.com
Adding only CONFIG_BT for Bluetooth support does not enable a lot of
the basic support expected from a Bluetooth stack, so adding more
generic Bluetooth support.
Partial fix for [YOCTO #6960].
Signed-off-by: Cristian Iorga cristian.io...@intel.com
From: Ng Wei Tee wei.tee...@intel.com
Hi all,
This patch is to enable Marvell Wifi and Bluetooth driver support
in valleyisland-32.scc and valleyisland.scc.
Valley Island BSP does not have Wifi and Bluetooth driver support.
We used the configs available in bluetooth.cfg and bluetooth-usb.cfg
to
From: Ng Wei Tee wei.tee...@intel.com
This commit adds the new features/mwifiex/mwifiex.cfg and mwifiex.scc
to support Marwell wifi features.
Signed-off-by: Ng Wei Tee wei.tee...@intel.com
---
meta/cfg/kernel-cache/features/mwifiex/mwifiex.cfg |7 +++
From: Ng Wei Tee wei.tee...@intel.com
Hi all,
This patch is to backport Braswell bug fixes patches that are
available in the upstream kernel into Yocto Project linux kernel
v3.19. These fixes are related to GFX's DRM/i915 kernel module.
The fixes here fix the following scenario:
1. X11 Matchbox
From: Rafael J. Wysocki rafael.j.wyso...@intel.com
Add an -enter_freeze callback routine, intel_idle_freeze(), to
the intel_idle driver and point the -enter_freeze callback
pointers of all of the driver's state objects to it.
Signed-off-by: Rafael J. Wysocki rafael.j.wyso...@intel.com
Acked-by:
From: Rafael J. Wysocki rafael.j.wyso...@intel.com
The efficiency of suspend-to-idle depends on being able to keep CPUs
in the deepest available idle states for as much time as possible.
Ideally, they should only be brought out of idle by system wakeup
interrupts.
However, timer interrupts
From: Len Brown len.br...@intel.com
Support C-states for the Airmont core in the Cherrytrail and Braswell SOCs.
The states are similar to those of Silvermont in Baytrail,
except both flavors of C6 states are faster.
Signed-off-by: Len Brown len.br...@intel.com
Cc: Kumar P Mahesh
From: Len Brown len.br...@intel.com
On some Silvermont-Core/Baytrail-SOC systems,
C1E latency is higher than original specifications.
Although C1E is still enumerated in CPUID.MWAIT.EDX,
we delete the state from intel_idle to avoid latency impact.
Under some conditions, the latency of the
From: Ng Wei Tee wei.tee...@intel.com
Hi all,
This patch is to backport Braswell intel_idle driver patches that are
available in the upstream kernel into Yocto Project linux kernel v3.19.
These patches are to enable intel_idle driver to support C-states for
the Airmont core in the Cherrytrail
From: Ville Syrjälä ville.syrj...@linux.intel.com
Set up the chv display PHY lane stagger registers according to
Programming Guide for 1273 CHV eDP/DP/HDMI Display PHY v1.04
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Reviewed-by: Deepak S deepa...@linux.intel.com
Signed-off-by:
From: Ng Wei Tee wei.tee...@intel.com
Hi all,
This patch is to backport Braswell bug fixes patches that are
available in the upstream kernel into Yocto Project linux
kernel v3.19. These fixes are related to GFX's DRM/i915 kernel
module.
The fixes here fix the following scenarios:
1. Fixes for
From: Ville Syrjälä ville.syrj...@linux.intel.com
Sometimes (exactly when is a bit unclear) DISPLAY_PHY_CONTROL appears to
get corrupted. The values I've managed to read from it seem to have some
pattern but vary quite a lot. The corruption doesn't seem to just happen
when the register is
From: Ville Syrjälä ville.syrj...@linux.intel.com
With recent hardware/firmware there don't appear to be any glitches
on the other PHY when we toggle the cmnreset for the other PHY. So
detangle the cmnlane power wells from one another and let them be
controlled independently.
This reverts commit
From: Ng Wei Tee wei.tee...@intel.com
Hi all,
This patch is to backport Braswell bug fixes patches that are
available in the upstream kernel into Yocto Project linux kernel
v3.19. These fixes are related to GFX's DRM/i915 kernel module.
The fixes here fix the following scenarios:-
1) Single
From: Ng Wei Tee wei.tee...@intel.com
Hi all,
Due to the broken issues of the series in the previous submission,
this patch is to solve the issue by choosing the right Braswell bug
fixes patches that are available in the upstream kernel into
Yocto Project linux kernel v3.19. These bug fix
From: Andy Shevchenko andriy.shevche...@linux.intel.com
Instead of using magic number in the code the patch provides
DW_DMA_MAX_NR_MASTERS constant.
While here, restrict the reading of data width array by amount of the actual
number of AHB masters.
Signed-off-by: Andy Shevchenko
From: Andy Shevchenko andriy.shevche...@linux.intel.com
The new DMAEngine requirement is to provide what the DMA controller can do,
such as directions, bus widths, and residue granularity. The patch sets those
properties for the DesignWare DMA controller driver.
Signed-off-by: Andy Shevchenko
From: David Box david.e@linux.intel.com
This patch implements an I2C bus sharing mechanism between the host and platform
hardware on select Intel BayTrail SoC platforms using the X-Powers AXP288 PMIC.
On these platforms access to the PMIC must be shared with platform hardware. The
hardware
From: Nicholas Mc Guire hof...@osadl.org
return type of wait_for_completion_timeout is unsigned long not int, rather
than introducing a new variable the wait_for_completion_timeout is moved
into the if condition as the return value is only used to detect timeout.
Signed-off-by: Nicholas Mc Guire
From: Desmond Liu desmo...@broadcom.com
Fixed behaviour of get_mctrl() serial driver function as documented in:
https://www.kernel.org/doc/Documentation/serial/driver
Added device-tree properties 'dcd-override', 'dsr-override',
'cts-override', and 'ri-override' specific to the Synopsis 8250
From: Jisheng Zhang jszh...@marvell.com
readl/writel is too expensive especially on Cortex A9 w/ outer L2 cache.
This introduces i2c read/write delays on Marvell BG2/BG2Q SoCs when there
are heavy L2 cache maintenance operations at the same time.
The driver does not perform DMA, so it's safe to
From: David Box david.e@linux.intel.com
Adds support for acquiring and releasing a hardware bus lock in the i2c
designware core transfer function. This is needed for i2c bus controllers
that are shared with but not controlled by the kernel.
Signed-off-by: David E. Box
From: Andy Shevchenko andriy.shevche...@linux.intel.com
The clk_khz field makes sense only if SS counters are not provided. Since we
provide them for Haswell and Baytrail explicitly we may omit the clk_khz
parameter.
Reviewed-by: Jarkko Nikula jarkko.nik...@linux.intel.com
Signed-off-by: Andy
From: Feng Kan f...@apm.com
Enable APM X-Gene SoC serial port functionality when using ACPI table to
initialize serial port.
Signed-off-by: Feng Kan f...@apm.com
Signed-off-by: Greg Kroah-Hartman gre...@linuxfoundation.org
(cherry picked from commit 5e1aeea52f6a0763e79473b1767401fda88eb7e1)
From: Ng Wei Tee wei.tee...@intel.com
Hi all,
This patch series is to backport Braswell bug fixes and feature
improvement patches from upstream kernel into Yocto Project linux
kernel v3.19. These back-ported patches had include I/O drivers such
as HS-UART, I2C, SMBUS i801, Pinctrl driver, ACPI
From: Jiang Liu jiang@linux.intel.com
Enable support of IOAPIC hotplug by:
1) reintroducing ACPI based IOAPIC driver
2) enhance pci_root driver to hook hotplug events
The ACPI IOAPIC driver is always enabled if all of ACPI, PCI and IOAPIC
are enabled.
Signed-off-by: Jiang Liu
From: Mika Westerberg mika.westerb...@linux.intel.com
Zotac ZBOX PI320, a Baytrail based mini-PC, has power button connected to a
GPIO pin and it is exposed to the operating system as Windows 8 button
array. This is implemented in Linux as a driver using gpio_keys.
However, BIOS on this
From: Mika Westerberg mika.westerb...@linux.intel.com
Before resuming from system sleep BIOS restores its view of pin
configuration. If we have configured some pins differently from that, for
instance some driver requested a pin as a GPIO but it was not in GPIO mode
originally, our view of the
From: Mika Westerberg mika.westerb...@linux.intel.com
The BIOS might reconfigure pins as it needs when S3 is entered. This might
cause drivers using the GPIOs to fail because the state was wrong or
interrupts stopped working.
Fix this by saving and restoring enough pin context over system sleep.
From: Wolfram Sang w...@the-dreams.de
This platform_driver does not need to set an owner, it will be populated by the
driver core.
Signed-off-by: Wolfram Sang w...@the-dreams.de
Acked-by: Mika Westerberg mika.westerb...@linux.intel.com
Signed-off-by: Linus Walleij linus.wall...@linaro.org
From: Len Brown len.br...@intel.com
Support C-states for the Airmont core in the Cherrytrail and Braswell SOCs.
The states are similar to those of Silvermont in Baytrail,
except both flavors of C6 states are faster.
Signed-off-by: Len Brown len.br...@intel.com
Cc: Kumar P Mahesh
From: Mika Westerberg mika.westerb...@linux.intel.com
If the pin is in HiZ mode when it is requested as GPIO its value cannot be
read (it always returns 0). In order to cope with the Linux GPIO subsystem
where we do not have such state at all, turn the pin to be input instead.
Reported-by:
From: Heikki Krogerus heikki.kroge...@linux.intel.com
If it fails we have to skip the device.
Signed-off-by: Heikki Krogerus heikki.kroge...@linux.intel.com
Signed-off-by: Rafael J. Wysocki rafael.j.wyso...@intel.com
(cherry picked from commit 4483d59e29fea65ef428be92a866aed50e28c795)
From: Wang YanQing udkni...@gmail.com
Commit 8b5c913f7ee6464849570bacb6bcd9ef0eaf7dce
(serial: 8250_pci: Add WCH CH352 quirk to avoid Xscale detection)
trigger one redundant entry report message.
This patch fix it.
Reported-by: Russell King r...@arm.linux.org.uk
Signed-off-by: Wang YanQing
From: Heikki Krogerus heikki.kroge...@linux.intel.com
Signed-off-by: Heikki Krogerus heikki.kroge...@linux.intel.com
Signed-off-by: Greg Kroah-Hartman gre...@linuxfoundation.org
(cherry picked from commit 0a0d412abe473c37ddec8d3f6c0b84c58f1bb061)
Signed-off-by: Ng Wei Tee wei.tee...@intel.com
From: Wang YanQing udkni...@gmail.com
These quirk entries have the same effect as default
quirk entry, so we can just delete them.
Signed-off-by: Wang YanQing udkni...@gmail.com
Signed-off-by: Greg Kroah-Hartman gre...@linuxfoundation.org
(cherry picked from commit
From: qipeng.zha qipeng@intel.com
From the comments of gpiod_direction_output(), need to set @value
as initial output, so update the lowlevel routine to make it work.
Signed-off-by: jason.cj.chenjason.cj.c...@intel.com
Signed-off-by: qipeng.zha qipeng@intel.com
Acked-by: Mika Westerberg
From: Jarkko Nikula jarkko.nik...@linux.intel.com
This simplifies the error and remove paths.
Signed-off-by: Jarkko Nikula jarkko.nik...@linux.intel.com
Reviewed-by: Jean Delvare jdelv...@suse.de
Signed-off-by: Wolfram Sang w...@the-dreams.de
(cherry picked from commit
From: Alexey Brodkin alexey.brod...@synopsys.com
With -EPROBE_DEFER, this message is confusing and we hope for a
centralized printout in the future anyhow.
Signed-off-by: Alexey Brodkin abrod...@synopsys.com
Acked-by: Mika Westerberg mika.westerb...@linux.intel.com
Acked-by: Christian Ruppert
From: Jarkko Nikula jarkko.nik...@linux.intel.com
Simplifies the code a bit and makes easier to disable PCI device on driver
detach by removing the pcim_pin_device() call in the future if needed.
Reason why i2c-i801.c doesn't ever call pci_disable_device() was because it
made some systems to
From: Ng Wei Tee wei.tee...@intel.com
Include the Braswell SoC feature in the two intel-common BSPs. The
Braswell SoC is used in both 32 and 64 bit environments.
Signed-off-by: Ng Wei Tee wei.tee...@intel.com
---
.../bsp/intel-common/intel-core2-32.scc|1 +
From: Ng Wei Tee wei.tee...@intel.com
Add support for the devices on the Braswell SoCs, including
i915 graphic support.
Signed-off-by: Ng Wei Tee wei.tee...@intel.com
---
.../features/soc/braswell/braswell.cfg |1 +
.../features/soc/braswell/braswell.scc |6
From: Ng Wei Tee wei.tee...@intel.com
Hi all,
This patch is to add support for devices on Braswell SoC in
intel-common layer. A new braswell folder was created under
features/soc/ to store the braswell.scc and braswell.cfg. When
we are building kernel for a preliminary hardware target, the
From: Ng Wei Tee wei.tee...@intel.com
Hi all,
During system resume, improper setup of event buffer will leads
to bus access errors. This patch is back-ported to fix the issue
mentioned above. The patch was back-ported from upstream kernel
into linux-yocto-3.10.
It was built with Valley Island
From: Roger Quadros rog...@ti.com
During system resume, if the event buffers are not setup before
the gadget controller starts then we start with invalid context
and this can lead to bus access errors. This is especially true for
platforms that loose the controller context during system suspend.
From: Ng Wei Tee wei.tee...@intel.com
Hi all,
The kernel complains that 'too much work for irq' when HSUART is
stressed in PCI mode. This 2 patches are back-ported to fix the
issue mentioned above. The patches were back-ported from upstream
kernel into linux-yocto-3.10.
It was built with Valley
From: Heikki Krogerus heikki.kroge...@linux.intel.com
It should not be used together with Auto Flow Control, and
Auto Flow Control is always enabled on Baytrail.
Signed-off-by: Heikki Krogerus heikki.kroge...@linux.intel.com
Signed-off-by: Greg Kroah-Hartman gre...@linuxfoundation.org
(cherry
From: Ng, Wei Tee wei.tee...@intel.com
Hi all,
This patch is to enable Realtek Ethernet Driver support
in valleyisland-32.scc. Valley Island BSP does not support
this driver by default. We used the common-pc-eth.scc to
turn on the driver configuration.
This configuration was built and tested
From: Ng, Wei Tee wei.tee...@intel.com
Valley Island BSP does not have Realtek ethernet driver support.
This patch will enabled Realtek ethernet driver by using configs
available in common-pc-eth.cfg.
Signed-off-by: Ng, Wei Tee wei.tee...@intel.com
---
From: Ng, Wei Tee wei.tee...@intel.com
Hi all,
This patch is to enable Realtek Ethernet driver support
in valleyisland.scc. Valley Island BSP does not support
this driver by default, we used the common-pc-eth.scc to
turn on the driver configuration.
This configuration was built and tested
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