Dear Nick,
Can you inform how the way gate-bias is considered in the next release
of TranSIESTA so that TranSIESTA users can have an overview of this
functional in advance.
Thanks so much.
Guangping Zhang
On 2015/7/26 21:13, Nick Papior wrote:
I cannot say for sure, I hope before the end of the year...
--
Kind regards Nick Papior
On 26 Jul 2015 18:01, "Nayereh Ghobadi" <[email protected]
<mailto:[email protected]>> wrote:
Thank you very much for your reply. It will be very kind of you if
let me know when the next release of transiesta will be available?
On Sun, Jul 26, 2015 at 8:21 PM, Nick Papior <[email protected]
<mailto:[email protected]>> wrote:
Such calculations will be made available in the next release
of transiesta.
On 26 Jul 2015 15:34, "Nayereh Ghobadi" <[email protected]
<mailto:[email protected]>> wrote:
Dear Siesta users
I have used Transiesta to study a graphene based
transistor. I want to calculate the gate-bias modulation
effect on this structure. When I set the external electric
field perpendicular to the Z-direction along with
source-drain bias (TS.Voltage), I always get such warning:
WARNING: both ext. voltage and field !!
WARNING: will neglect voltage !!
It will be very kind of you if can help me.
Best regards,
Nayereh Ghobadi
