On 28/09/10 04:38, Richard A. Smith wrote: > I've got the latest HEAD built and I can sample data from the OLS. > My first attempt to run some data through the transitioncounter however, > gave me confusing output. > > When I run a small capture on a single channel and specify '-a > transitioncounter' the analyzer seems to run _before_ the capture > happens. ie I get transition analysis at the same time the LED moves to > armed. Then when I trigger I get my sampled output.
The protocol decoder setup is really unfinished right now, it's more a proof of concept. It'll be a while before that's fully functional, it's quite a bit of work. > Also the wiki claims that RLE mode is supported but currently unused. > Whats necessary to turn that into "used"? Some testing etc... I was waiting for the RLE code in the FPGA firmware to stabilize, there was some talk about it breaking at some point. However as far as I know that should be ok now, so I'll be taking a look at it real soon. The external clock feature should mostly be a matter of enabling the functionality in the driver, no big deal. -- Bert Vermeulen [email protected] email/xmpp ------------------------------------------------------------------------------ Start uncovering the many advantages of virtual appliances and start using them to simplify application deployment and accelerate your shift to cloud computing. http://p.sf.net/sfu/novell-sfdev2dev _______________________________________________ sigrok-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/sigrok-devel
