Hi All,
I was looking through sr commit logs this morning, and I saw the release
commits. Congratulations to everyone. Great work. Fantastic job!
So now we've released, I wanted to share my thoughts for coming
development.
First off, it has been said may times before, so we know the v0.3 cycle was
very long. Though there were some special circumstances, I think it would
be good to release earlier and more often in the coming cycles. Would a
4-month cycle be possible? Could we conceivably release v0.4 in August?
Second, if everyone is happy, I would like to delete (or at least disable)
the saleae driver now, so that we can give fx2lafw the maximum level of
testing. Is everyone happy if I go ahead and do that within the next couple
of days?
Third, biot: what state is your analog work in? Are you working in a
branch? Is it going into the mainline any time soon? If so I can begin to
integrate the Fx2 analog stuff with that.
Fourth, who owns the Braintechnology USB-LPS and the Saleae Logic16? I
guess the USB-LPS would be easy to add support for if someone wants to work
with me on that. I just need to add a new sampling mode to fx2lafw, along
with analog support. The Logic16 must have some kind of CPLD on it's front
end. Has anyone had a look inside one of these?
Fifth, I'm interested in possibilities for making libsigrok more threaded
with a FIFO of buffers inside to solve buffer overflow problems that we
experience with Fx2s. This would allow us to do away with the fixed number
of transfer buffers in the fx2lafw driver, and just allocate more as we
need them (up to some limit), and the front ends can consume them as fast
as they can, but without having to keep up. Correct me if I'm wrong, but
from my knowledge of libsigrok this doesn't sound as hard as it could be.
Has anyone made any plans to tackle this? I'm quite busy, but I might be
able to have a go some time.
So those are my thoughts.
Once again, congratulations everyone.
Joel
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