Hi,
I'd like to propose an enhancement to the SPI protocol decoder: The
decoder waits for a H-L transition on CS#, before it starts decoding. If
CS# goes high before the provided number of bits are received, the bits
decoded so far are discarded.
I attached a diff file; maybe you are interested...
Regards - Clemens
diff --git a/mine-spi/pd.py b/libsigrokdecode/decoders/spi/pd.py
index eb51c89..3816659 100644
--- a/mine-spi/pd.py
+++ b/libsigrokdecode/decoders/spi/pd.py
@@ -19,9 +19,6 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-# sigrok-cli -i spi_atmega32_00_play.sr -P mine:wordsize=8:miso=1:mosi=1:sck=2:cs=0 | less
-
-
# SPI protocol decoder
import sigrokdecode as srd
@@ -41,8 +38,8 @@ ANN_HEX = 0
class Decoder(srd.Decoder):
api_version = 1
- id = 'mine'
- name = 'MINE'
+ id = 'spi'
+ name = 'SPI'
longname = 'Serial Peripheral Interface'
desc = 'Full-duplex, synchronous, serial bus.'
license = 'gplv2+'
@@ -78,7 +75,6 @@ class Decoder(srd.Decoder):
self.cs_was_deasserted_during_data_word = 0
self.oldcs = -1
self.oldpins = None
- self.state = "stop"
def start(self, metadata):
self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
@@ -101,81 +97,70 @@ class Decoder(srd.Decoder):
self.put(self.samplenum, self.samplenum, self.out_proto,
['CS-CHANGE', self.oldcs, cs])
self.put(self.samplenum, self.samplenum, self.out_ann,
- [0, ['CS-CHANGE @ %d: %d->%d' % (self.samplenum, self.oldcs, cs)]])
+ [0, ['CS-CHANGE: %d->%d' % (self.oldcs, cs)]])
self.oldcs = cs
- if cs == 0:
- self.state = "start"
- if cs == 1:
- self.state = "stop"
- # Reset decoder state.
- self.mosidata = 0
- self.misodata = 0
- self.bitcount = 0
- continue
-
# Ignore sample if the clock pin hasn't changed.
if sck == self.oldsck:
continue
- if self.state == "start":
-
- self.oldsck = sck
-
- # Sample data on rising/falling clock edge (depends on mode).
- mode = spi_mode[self.options['cpol'], self.options['cpha']]
- if mode == 0 and sck == 0: # Sample on rising clock edge
- continue
- elif mode == 1 and sck == 1: # Sample on falling clock edge
- continue
- elif mode == 2 and sck == 1: # Sample on falling clock edge
- continue
- elif mode == 3 and sck == 0: # Sample on rising clock edge
- continue
-
- # If this is the first bit, save its sample number.
- if self.bitcount == 0:
- self.start_sample = self.samplenum
- active_low = (self.options['cs_polarity'] == 'active-low')
- deasserted = cs if active_low else not cs
- if deasserted:
- self.cs_was_deasserted_during_data_word = 1
-
- ws = self.options['wordsize']
-
- # Receive MOSI bit into our shift register.
- if self.options['bitorder'] == 'msb-first':
- self.mosidata |= mosi << (ws - 1 - self.bitcount)
- else:
- self.mosidata |= mosi << self.bitcount
-
- # Receive MISO bit into our shift register.
- if self.options['bitorder'] == 'msb-first':
- self.misodata |= miso << (ws - 1 - self.bitcount)
- else:
- self.misodata |= miso << self.bitcount
-
- self.bitcount += 1
-
- # Continue to receive if not enough bits were received, yet.
- if self.bitcount != ws:
+ self.oldsck = sck
+
+ # Sample data on rising/falling clock edge (depends on mode).
+ mode = spi_mode[self.options['cpol'], self.options['cpha']]
+ if mode == 0 and sck == 0: # Sample on rising clock edge
continue
-
- self.put(self.start_sample, self.samplenum, self.out_proto,
- ['DATA', self.mosidata, self.misodata])
+ elif mode == 1 and sck == 1: # Sample on falling clock edge
+ continue
+ elif mode == 2 and sck == 1: # Sample on falling clock edge
+ continue
+ elif mode == 3 and sck == 0: # Sample on rising clock edge
+ continue
+
+ # If this is the first bit, save its sample number.
+ if self.bitcount == 0:
+ self.start_sample = self.samplenum
+ active_low = (self.options['cs_polarity'] == 'active-low')
+ deasserted = cs if active_low else not cs
+ if deasserted:
+ self.cs_was_deasserted_during_data_word = 1
+
+ ws = self.options['wordsize']
+
+ # Receive MOSI bit into our shift register.
+ if self.options['bitorder'] == 'msb-first':
+ self.mosidata |= mosi << (ws - 1 - self.bitcount)
+ else:
+ self.mosidata |= mosi << self.bitcount
+
+ # Receive MISO bit into our shift register.
+ if self.options['bitorder'] == 'msb-first':
+ self.misodata |= miso << (ws - 1 - self.bitcount)
+ else:
+ self.misodata |= miso << self.bitcount
+
+ self.bitcount += 1
+
+ # Continue to receive if not enough bits were received, yet.
+ if self.bitcount != ws:
+ continue
+
+ self.put(self.start_sample, self.samplenum, self.out_proto,
+ ['DATA', self.mosidata, self.misodata])
+ self.put(self.start_sample, self.samplenum, self.out_ann,
+ [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
+ self.misodata)]])
+
+ if self.cs_was_deasserted_during_data_word:
self.put(self.start_sample, self.samplenum, self.out_ann,
- [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x, StartSample: %d, StopSample: %d' % (self.mosidata,
- self.misodata, self.start_sample, self.samplenum)]])
-
- if self.cs_was_deasserted_during_data_word:
- self.put(self.start_sample, self.samplenum, self.out_ann,
- [ANN_HEX, ['WARNING: CS# was deasserted during this '
- 'SPI data byte!']])
-
- # Reset decoder state.
- self.mosidata = 0
- self.misodata = 0
- self.bitcount = 0
-
- # Keep stats for summary.
- self.bytesreceived += 1
+ [ANN_HEX, ['WARNING: CS# was deasserted during this '
+ 'SPI data byte!']])
+
+ # Reset decoder state.
+ self.mosidata = 0
+ self.misodata = 0
+ self.bitcount = 0
+
+ # Keep stats for summary.
+ self.bytesreceived += 1
+
------------------------------------------------------------------------------
See everything from the browser to the database with AppDynamics
Get end-to-end visibility with application monitoring from AppDynamics
Isolate bottlenecks and diagnose root cause in seconds.
Start your free trial of AppDynamics Pro today!
http://pubads.g.doubleclick.net/gampad/clk?id=48808831&iu=/4140/ostg.clktrk
_______________________________________________
sigrok-devel mailing list
[email protected]
https://lists.sourceforge.net/lists/listinfo/sigrok-devel
