Hi devs, Yesterday I got pointed to sigrok after writing pyla as a 2-weekend hack: https://github.com/zwizwa/pyla I had used the saleae library before in an ad-hoc way for some iso7816 sniffing https://github.com/zwizwa/sl-apdu so this was an attempt to clean it up a bit.
I was wondering if anyone has any ideas about how i can integrate pyla or have it be absorbed in the sigrok project. I don't see the point in me doing things different for just the sake of it.. Some of the ideas behind pyla: - Performant enough to do real time protocol analysis for a couple of spi ports and uarts in parallel on my 2 year old laptop, running the Saleae 8-port at 24MHz. In practice this means C++ (or C) for the frontend. Python is fine after the bytes have been parsed. - C++ interface for writing the procotol analyzers is (and should stay) really simple. Currently it uses std::vector of bytes in and out. The analyzer code is abstracted in such a way that it can also run on a bare-bones or RTOS microcontroller in a DMA ISR to side-step the high bandwidth data transport to PC problem. - Use swig to automate wrapping to python so python can be used for ad-hoc parsing after the core protocol analysis is done. I like the python generators for writing ad-hoc debug scripts. - Allow for dataflow composition of C++ analyzer modules without having to go through Python code. Also still thinking about running this part on a bare-bones or RTOS microcontroller. For this a "branchless" dataflow mini-Forth is used. Cheers Tom ------------------------------------------------------------------------------ Learn Graph Databases - Download FREE O'Reilly Book "Graph Databases" is the definitive new guide to graph databases and their applications. Written by three acclaimed leaders in the field, this first edition is now available. Download your free book today! http://p.sf.net/sfu/13534_NeoTech _______________________________________________ sigrok-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/sigrok-devel
