Pull out the code which switches Sigma from the FPGA programming mode into Logic-Analyzer mode into separate function. Also, given the reply is only ever 3-byte long, do not allocate 32 byte big buffer, but only a 3-byte long one.
Signed-off-by: Marek Vasut <[email protected]> --- hardware/asix-sigma/asix-sigma.c | 52 +++++++++++++++++++++++++++------------- 1 file changed, 35 insertions(+), 17 deletions(-) diff --git a/hardware/asix-sigma/asix-sigma.c b/hardware/asix-sigma/asix-sigma.c index 8e79403..06373d6 100644 --- a/hardware/asix-sigma/asix-sigma.c +++ b/hardware/asix-sigma/asix-sigma.c @@ -80,12 +80,6 @@ static const int32_t hwcaps[] = { SR_CONF_LIMIT_SAMPLES, }; -/* Initialize the logic analyzer mode. */ -static uint8_t logic_mode_start[] = { - 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, - 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, -}; - static const char *sigma_firmware_files[] = { /* 50 MHz, supports 8 bit fractions */ FIRMWARE_DIR "/asix-sigma-50.fw", @@ -455,6 +449,37 @@ static int sigma_fpga_init_bitbang(struct dev_context *devc) } /* + * Configure the FPGA for logic-analyzer mode. + */ +static int sigma_fpga_init_la(struct dev_context *devc) +{ + /* Initialize the logic analyzer mode. */ + uint8_t logic_mode_start[] = { + 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, + 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, + }; + + uint8_t result[3]; + int ret; + + /* Initialize the logic analyzer mode. */ + sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); + + /* Expect a 3 byte reply. */ + ret = sigma_read(result, 3, devc); + if (ret != 3) + goto err; + + if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) + goto err; + + return SR_OK; +err: + sr_err("Configuration failed. Invalid reply received."); + return SR_ERR; +} + +/* * Read the firmware from a file and transform it into a series of bitbang * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d * by the caller of this function. @@ -532,7 +557,6 @@ static int upload_firmware(int firmware_idx, struct dev_context *devc) unsigned char *buf; unsigned char pins; size_t buf_size; - unsigned char result[32]; const char *firmware = sigma_firmware_files[firmware_idx]; struct ftdi_context *ftdic = &devc->ftdic; @@ -592,16 +616,10 @@ static int upload_firmware(int firmware_idx, struct dev_context *devc) while (sigma_read(&pins, 1, devc) == 1) ; - /* Initialize the logic analyzer mode. */ - sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); - - /* Expect a 3 byte reply. */ - ret = sigma_read(result, 3, devc); - if (ret != 3 || - result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { - sr_err("Configuration failed. Invalid reply received."); - return SR_ERR; - } + /* Initialize the FPGA for logic-analyzer mode. */ + ret = sigma_fpga_init_la(devc); + if (ret != SR_OK) + return ret; devc->cur_firmware = firmware_idx; -- 1.8.5.3 ------------------------------------------------------------------------------ Start Your Social Network Today - Download eXo Platform Build your Enterprise Intranet with eXo Platform Software Java Based Open Source Intranet - Social, Extensible, Cloud Ready Get Started Now And Turn Your Intranet Into A Collaboration Platform http://p.sf.net/sfu/ExoPlatform _______________________________________________ sigrok-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/sigrok-devel
