My first attempt at using git and creating a patch for some small
incremental DSLogic support.

Regards /// Carl-Fredrik

diff --git a/src/hardware/fx2lafw/api.c b/src/hardware/fx2lafw/api.c
index 04284e5..e1c830d 100644
--- a/src/hardware/fx2lafw/api.c
+++ b/src/hardware/fx2lafw/api.c
@@ -20,6 +20,9 @@

 #include "protocol.h"
 #include "dslogic.h"
+#include "libsigrok.h"
+#include "libsigrok-internal.h"
+

 static const struct fx2lafw_profile supported_fx2[] = {
     /*
@@ -519,6 +522,18 @@ static int config_set(uint32_t key, GVariant *data,
const struct sr_dev_inst *sd
     switch (key) {
     case SR_CONF_SAMPLERATE:
         arg = g_variant_get_uint64(data);
+
+        if(strcmp(sdi->model, "DSLogic") == 0 && strcmp(sdi->vendor,
"DreamSourceLab") == 0) {
+            for (i = 0; i < ARRAY_SIZE(dslogic_samplerates); i++) {
+                if (dslogic_samplerates[i] == arg) {
+                    devc->cur_samplerate = arg;
+                    break;
+                }
+            }
+            if (i == ARRAY_SIZE(dslogic_samplerates))
+                ret = SR_ERR_ARG;
+        }
+        else {
         for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
             if (samplerates[i] == arg) {
                 devc->cur_samplerate = arg;
@@ -527,6 +542,7 @@ static int config_set(uint32_t key, GVariant *data,
const struct sr_dev_inst *sd
         }
         if (i == ARRAY_SIZE(samplerates))
             ret = SR_ERR_ARG;
+        }
         break;
     case SR_CONF_LIMIT_SAMPLES:
         devc->limit_samples = g_variant_get_uint64(data);
diff --git a/src/hardware/fx2lafw/protocol.h
b/src/hardware/fx2lafw/protocol.h
index 3be8718..1b1664f 100644
--- a/src/hardware/fx2lafw/protocol.h
+++ b/src/hardware/fx2lafw/protocol.h
@@ -55,8 +55,8 @@

 /* Protocol commands */
 #define CMD_GET_FW_VERSION        0xb0
-#define CMD_START            0xb1
-#define CMD_GET_REVID_VERSION        0xb2
+#define CMD_GET_REVID_VERSION        0xb1
+#define CMD_START            0xb2

 #define CMD_START_FLAGS_WIDE_POS    5
 #define CMD_START_FLAGS_CLK_SRC_POS    6
------------------------------------------------------------------------------
BPM Camp - Free Virtual Workshop May 6th at 10am PDT/1PM EDT
Develop your own process in accordance with the BPMN 2 standard
Learn Process modeling best practices with Bonita BPM through live exercises
http://www.bonitasoft.com/be-part-of-it/events/bpm-camp-virtual- event?utm_
source=Sourceforge_BPM_Camp_5_6_15&utm_medium=email&utm_campaign=VA_SF
_______________________________________________
sigrok-devel mailing list
sigrok-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/sigrok-devel

Reply via email to